iMX target config script's ported from Freescale BSP.

[openocd.git] / tcl / board / imx31pdk.cfg

diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index e000e3cc69f5205739140cd2b49a7908bb3cf94d..4dfa4db60145d2f8e3a9284bbc3e21e8f96cb0be 100644 (file)
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -1,59 +1,47 @@
 # The IMX31PDK eval board has a single IMX31 chip
 source [find target/imx31.cfg]
+source [find target/imx.cfg]
 $_TARGETNAME configure -event reset-init { imx31pdk_init }
 
 proc imx31pdk_init { } {
+
+       imx3x_reset
+
        # This setup puts RAM at 0x80000000
 
-       # ========================================
-       # Init CCM
-       # ========================================
        mww 0x53FC0000 0x040
        mww 0x53F80000 0x074B0B7D
-
-       sleep 100
-
-       # ========================================
+       
        # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
-       # ========================================
-       mww 0x53F80004 0xFF871D50
-       mww 0x53F80010 0x00271C1B
-
-       # ========================================
-       # Configure CPLD on CS5
-       # ========================================
-       mww 0xb8002050 0x0000DCF6
-       mww 0xb8002054 0x444A4541
-       mww 0xb8002058 0x44443302
-
-       # ========================================
+       #mww 0x53F80004 0xFF871D50
+       #mww 0x53F80010 0x00271C1B
+       
+       # Start 16 bit NorFlash Initialization on CS0
+       mww 0xb8002000 0x0000CC03
+       mww 0xb8002004 0xa0330D01
+       mww 0xb8002008 0x00220800
+       
+       # Configure CPLD on CS4
+       mww 0xb8002040 0x0000DCF6
+       mww 0xb8002044 0x444A4541
+       mww 0xb8002048 0x44443302
+       
        # SDCLK
-       # ========================================
        mww 0x43FAC26C 0
-
-       # ========================================
+       
        # CAS
-       # ========================================
        mww 0x43FAC270 0
-
-       # ========================================
+       
        # RAS
-       # ========================================
        mww 0x43FAC274 0
-
-       # ========================================
+       
        # CS2 (CSD0)
-       # ========================================
        mww 0x43FAC27C 0x1000
-
-       # ========================================
+       
        # DQM3
-       # ========================================
        mww 0x43FAC284 0
-
-       # ========================================
+       
        # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
-       # ========================================
        mww 0x43FAC288 0
        mww 0x43FAC28C 0
        mww 0x43FAC290 0
@@ -76,10 +64,8 @@ proc imx31pdk_init { } {
        mww 0x43FAC2D4 0
        mww 0x43FAC2D8 0
        mww 0x43FAC2DC 0
-
-       # ========================================
-       # Initialization script for 32 bit DDR on MX31 PDK
-       # ========================================
+       
+       # Initialization script for 32 bit DDR on MX31 ADS
        mww 0xB8001010 0x00000004
        mww 0xB8001004 0x006ac73a
        mww 0xB8001000 0x92100000