TCL: fix non TCL comments

[openocd.git] / tcl / board / at91sam9g20-ek.cfg

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 15a9caf2889c5cadb9f0d22e6c50263b8c0bc9cb..deb4da1540cae3b47d99440d79c755d0920ac5db 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -80,10 +80,10 @@ proc at91sam9g20_reset_start { } {
        # jtag speed without causing GDB keep alive problem.
 
        arm7_9 fast_memory_access disable
-       adapter_khz 2                   # Slow-speed oscillator enabled at reset, so run jtag speed slow.
-       halt                            # Make sure processor is halted, or error will result in following steps.
+       adapter_khz 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+       halt                            ;# Make sure processor is halted, or error will result in following steps.
        wait_halt 10000
-       mww 0xfffffd08 0xa5000501       # RSTC_MR : enable user reset.
+       mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
 }
 
 proc at91sam9g20_reset_init { } {
@@ -97,7 +97,7 @@ proc at91sam9g20_reset_init { } {
        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
 
-       mww 0xfffffd44 0x00008000       # WDT_MR : disable watchdog.
+       mww 0xfffffd44 0x00008000       ;# WDT_MR : disable watchdog.
 
        # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
        # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
@@ -155,11 +155,11 @@ proc at91sam9g20_reset_init { } {
        # a number of registers.  The first step involves setting up the general I/O pins on the processor
        # to be able to interface and support the external memory.
 
-       mww 0xfffffc10 0x00000010       # PMC_PCER : enable PIOC clock
-       mww 0xfffff800 0x00006000       # PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
-       mww 0xfffff810 0x00004000       # PIOC_OER : enable output on 14
-       mww 0xfffff814 0x00002000       # PIOC_ODR : disable output on 13
-       mww 0xfffff830 0x00004000       # PIOC_SODR : set 14 to disable NAND
+       mww 0xfffffc10 0x00000010       ;# PMC_PCER : enable PIOC clock
+       mww 0xfffff800 0x00006000       ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+       mww 0xfffff810 0x00004000       ;# PIOC_OER : enable output on 14
+       mww 0xfffff814 0x00002000       ;# PIOC_ODR : disable output on 13
+       mww 0xfffff830 0x00004000       ;# PIOC_SODR : set 14 to disable NAND
 
        # The exact physical timing characteristics for the memory type used on the current board
        # (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
@@ -167,13 +167,13 @@ proc at91sam9g20_reset_init { } {
        # is a little tedious to do here.  If you have questions about how to do this, Atmel has
        # a decent application note #6255B that covers this process. 
 
-       mww 0xffffec30 0x00020002       # SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
-       mww 0xffffec34 0x04040404       # SMC_PULSE3 : 4 clock cycle pulse for all signals
-       mww 0xffffec38 0x00070006       # SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
-       mww 0xffffec3C 0x00020003       # SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
+       mww 0xffffec30 0x00020002       ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+       mww 0xffffec34 0x04040404       ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+       mww 0xffffec38 0x00070006       ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+       mww 0xffffec3C 0x00020003       ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
    
-       mww 0xffffe800 0x00000001       # ECC_CR : reset the ECC parity registers
-       mww 0xffffe804 0x00000002       # ECC_MR : page size is 2112 words (word is 8 bits)
+       mww 0xffffe800 0x00000001       ;# ECC_CR : reset the ECC parity registers
+       mww 0xffffe804 0x00000002       ;# ECC_MR : page size is 2112 words (word is 8 bits)
 
        # Identify NandFlash bank 0.