jtag newtap change & huge manual update

[openocd.git] / src / target / target / lm3s6965.cfg

diff --git a/src/target/target/lm3s6965.cfg b/src/target/target/lm3s6965.cfg
index e1d38227a211d7450b1523fc80a038fdf7ea1a76..8fdc9c89ffb30956710ed8dbfa7090ec64cbcfec 100644 (file)
--- a/src/target/target/lm3s6965.cfg
+++ b/src/target/target/lm3s6965.cfg
@@ -1,5 +1,26 @@
 # script for luminary lm3s6965
 
+
+if { [info exists CHIPNAME] } {        
+   set  _CHIPNAME $CHIPNAME    
+} else {        
+   set  _CHIPNAME lm3s6965
+}
+
+if { [info exists ENDIAN] } {  
+   set  _ENDIAN $ENDIAN    
+} else {        
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
 # jtag speed
 jtag_khz 500
 
@@ -10,16 +31,17 @@ jtag_ntrst_delay 100
 reset_config srst_only
 
 #jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
 
 # the luminary variant causes a software reset rather than asserting SRST
 # this stops the debug registers from being cleared
 # this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
 
 # 4k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash configuration
 flash bank stellaris 0 0 0 0 0