mips: m4k alternate pracc code. Patch 1

[openocd.git] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index fb4c37624135c31a51a9bfd911e1877cb3722071..e91bd57b6d610a9ebbccb5d2281f55d6952afb2f 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -90,14 +90,14 @@ static int mips_m4k_debug_entry(struct target *target)
        /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
        mips_ejtag_config_step(ejtag_info, 0);
 
+       mips32_save_context(target);
+
        /* make sure break unit configured */
        mips32_configure_break_unit(target);
 
        /* attempt to find halt reason */
        mips_m4k_examine_debug_reason(target);
 
-       mips32_save_context(target);
-
        /* default to mips32 isa, it will be changed below if required */
        mips32->isa_mode = MIPS32_ISA_MIPS32;
 
@@ -558,12 +558,12 @@ static int mips_m4k_step(struct target *target, int current,
        /* registers are now invalid */
        register_cache_invalidate(mips32->core_cache);
 
+       LOG_DEBUG("target stepped ");
+       mips_m4k_debug_entry(target);
+
        if (breakpoint)
                mips_m4k_set_breakpoint(target, breakpoint);
 
-       LOG_DEBUG("target stepped ");
-
-       mips_m4k_debug_entry(target);
        target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
        return ERROR_OK;
@@ -1186,7 +1186,6 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 
                if (CMD_ARGC == 2) {
                        uint32_t value;
-
                        retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
                        if (retval != ERROR_OK) {
                                command_print(CMD_CTX,
@@ -1194,12 +1193,9 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
                                                cp0_reg);
                                return ERROR_OK;
                        }
-                       retval = jtag_execute_queue();
-                       if (retval != ERROR_OK)
-                               return retval;
-
                        command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
                                        cp0_reg, cp0_sel, value);
+
                } else if (CMD_ARGC == 3) {
                        uint32_t value;
                        COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
@@ -1276,6 +1272,29 @@ COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
        return ERROR_OK;
 }
 
+COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
+{
+       struct target *target = get_current_target(CMD_CTX);
+       struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+       struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+
+       if (CMD_ARGC == 1)
+               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay);
+       else if (CMD_ARGC > 1)
+                       return ERROR_COMMAND_SYNTAX_ERROR;
+
+       command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+       if (ejtag_info->scan_delay >= 20000000) {
+               ejtag_info->mode = 0;
+               command_print(CMD_CTX, "running in legacy mode");
+       } else {
+               ejtag_info->mode = 1;
+               command_print(CMD_CTX, "running in fast queued mode");
+       }
+
+       return ERROR_OK;
+}
+
 static const struct command_registration mips_m4k_exec_command_handlers[] = {
        {
                .name = "cp0",
@@ -1305,6 +1324,13 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = {
                .help = "display/fix current core played to gdb",
                .usage = "",
        },
+       {
+               .name = "scan_delay",
+               .handler = mips_m4k_handle_scan_delay_command,
+               .mode = COMMAND_ANY,
+               .help = "display/set scan delay in nano seconds",
+               .usage = "[value]",
+       },
        COMMAND_REGISTRATION_DONE
 };