/* read ejtag control reg */
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (retval != ERROR_OK)
+ return retval;
/* clear this bit before handling polling
* as after reset registers will read zero */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("Reset Detected");
}
{
if (mips_m4k->is_pic32mx)
{
- uint32_t mchip_cmd;
-
LOG_DEBUG("Using MTAP reset to reset processor...");
/* use microchip specific MTAP reset */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
- mchip_cmd = MCHP_ASERT_RST;
- mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
- mchip_cmd = MCHP_DE_ASSERT_RST;
- mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
+ mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
}
else
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
}
}
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
+ {
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
+ mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
+ mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+ }
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
{
return retval;
}
+
+ /**
+ * target_read_memory() gets us data in _target_ endianess.
+ * If we want to use this data on the host for comparisons with some macros
+ * we must first transform it to _host_ endianess using target_buffer_get_u32().
+ */
+ current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr);
+
if (current_instr == MIPS32_SDBBP)
{
if ((retval = target_write_memory(target, breakpoint->address, 4, 1,
if (ERROR_OK != retval)
return retval;
+ /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
+ /* endianness, but byte array should represent target endianness */
+ uint32_t i, t32;
+ uint16_t t16;
+ for(i = 0; i < (count*size); i += size)
+ {
+ switch(size)
+ {
+ case 4:
+ t32 = le_to_h_u32(&buffer[i]);
+ target_buffer_set_u32(target,&buffer[i], t32);
+ break;
+ case 2:
+ t16 = le_to_h_u16(&buffer[i]);
+ target_buffer_set_u16(target,&buffer[i], t16);
+ break;
+ }
+ }
+
return ERROR_OK;
}
static int mips_m4k_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
+ /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
+ /* endianness, but byte array represents target endianness */
+ uint8_t * t = NULL;
+ t = malloc(count * sizeof(uint32_t));
+ if (t == NULL)
+ {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ uint32_t i, t32;
+ uint16_t t16;
+ for(i = 0; i < (count*size); i += size)
+ {
+ switch(size)
+ {
+ case 4:
+ t32 = target_buffer_get_u32(target,&buffer[i]);
+ h_u32_to_le(&t[i], t32);
+ break;
+ case 2:
+ t16 = target_buffer_get_u16(target,&buffer[i]);
+ h_u16_to_le(&t[i], t16);
+ break;
+ }
+ }
+ buffer = t;
+
/* if noDMA off, use DMAACC mode for memory write */
+ int retval;
if (ejtag_info->impcode & EJTAG_IMP_NODMA)
- return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+ retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
else
- return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+ retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
+
+ if (t != NULL)
+ free(t);
+
+ if (ERROR_OK != retval)
+ return retval;
+
+ return ERROR_OK;
}
static int mips_m4k_init_target(struct command_context *cmd_ctx,
if (!target_was_examined(target))
{
- mips_ejtag_get_idcode(ejtag_info, &idcode);
+ retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
+ if (retval != ERROR_OK)
+ return retval;
ejtag_info->idcode = idcode;
if (((idcode >> 1) & 0x7FF) == 0x29)
}
static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
- uint32_t count, uint8_t *buffer)
+ uint32_t count, const uint8_t *buffer)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
- struct working_area *source;
int retval;
int write_t = 1;
if (address & 0x3u)
return ERROR_TARGET_UNALIGNED_ACCESS;
- /* Get memory for block write handler */
- retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
- if (retval != ERROR_OK)
+ if (mips32->fast_data_area == NULL)
{
- LOG_WARNING("No working area available, falling back to non-bulk write");
- return mips_m4k_write_memory(target, address, 4, count, buffer);
+ /* Get memory for block write handler
+ * we preserve this area between calls and gain a speed increase
+ * of about 3kb/sec when writing flash
+ * this will be released/nulled by the system when the target is resumed or reset */
+ retval = target_alloc_working_area(target,
+ MIPS32_FASTDATA_HANDLER_SIZE,
+ &mips32->fast_data_area);
+ if (retval != ERROR_OK)
+ {
+ LOG_WARNING("No working area available, falling back to non-bulk write");
+ return mips_m4k_write_memory(target, address, 4, count, buffer);
+ }
+
+ /* reset fastadata state so the algo get reloaded */
+ ejtag_info->fast_access_save = -1;
}
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
+ /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
+ /* but byte array represents target endianness */
+ uint8_t * t = NULL;
+ t = malloc(count * sizeof(uint32_t));
+ if (t == NULL)
{
- uint32_t i, t32;
- for(i = 0; i < (count * 4); i += 4)
- {
- t32 = be_to_h_u32((uint8_t *) &buffer[i]);
- h_u32_to_le(&buffer[i], t32);
- }
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ uint32_t i, t32;
+ for(i = 0; i < (count*4); i += 4)
+ {
+ t32 = target_buffer_get_u32(target,&buffer[i]);
+ h_u32_to_le(&t[i], t32);
}
+
+ retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
+ count, (uint32_t*) (void *)t);
+
+ if (t != NULL)
+ free(t);
- retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write_t, address,
- count, (uint32_t*) buffer);
if (retval != ERROR_OK)
{
/* FASTDATA access failed, try normal memory write */
retval = mips_m4k_write_memory(target, address, 4, count, buffer);
}
- if (source)
- target_free_working_area(target, source);
-
return retval;
}
Code Review / openocd.git / blobdiff