- correct the register hi/lo read - wrong way round

[openocd.git] / src / target / mips_ejtag.c

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 6e6bd934931387fff2bd6f9207c3d2a110e2c55e..c169c6f0682bb2f191fa6281e1e906313eb867e4 100644 (file)
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -164,8 +164,8 @@ int mips_ejtag_step_disable(mips_ejtag_t *ejtag_info)
                        MIPS32_MTC0(15,31,0),                                                   /* move $15 to COP0 DeSave */
                        MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),     /* $15 = MIPS32_PRACC_STACK */
                        MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
-                       MIPS32_SW(1,0,15),                                                              /* sw $2,($15) */
-                       MIPS32_SW(2,0,15),                                                              /* sw $3,($15) */
+                       MIPS32_SW(1,0,15),                                                              /* sw $1,($15) */
+                       MIPS32_SW(2,0,15),                                                              /* sw $2,($15) */
                        MIPS32_MFC0(1,23,0),                                                    /* move COP0 Debug to $1 */
                        MIPS32_LUI(2,0xFFFF),                                                   /* $2 = 0xfffffeff */
                        MIPS32_ORI(2,2,0xFEFF),
@@ -194,18 +194,19 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
 
 int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
 {
+       u32 ejtag_ctrl;
        jtag_add_end_state(TAP_RTI);
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
        
        /* set debug break bit */
-       ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK;
-       mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+       ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
        
        /* break bit will be cleared by hardware */
-       ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
-       mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-       LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
-       if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl);
+       if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
                LOG_DEBUG("Failed to enter Debug Mode!");
        
        return ERROR_OK;
@@ -234,7 +235,7 @@ int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
                        MIPS32_SW(2,0,15),                                                              /* sw $2,($15) */
                        MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)),  /* $1 = MIPS32_PRACC_PARAM_OUT */
                        MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
-                       MIPS32_MFC0(2,23,0),                                                    /* move COP0 Debug to $1 */
+                       MIPS32_MFC0(2,23,0),                                                    /* move COP0 Debug to $2 */
                        MIPS32_SW(2,0,1),
                        MIPS32_LW(2,0,15),
                        MIPS32_LW(1,0,15),