/***************************************************************************\r
- * Copyright (C) 2005 by Dominic Rath *\r
+ * Copyright (C) 2005, 2007 by Dominic Rath *\r
* Dominic.Rath@gmx.de *\r
* *\r
+ * Copyright (C) 2007 by Vincent Palatin *\r
+ * vincent.palatin_openocd@m4x.org *\r
+ * *\r
* This program is free software; you can redistribute it and/or modify *\r
* it under the terms of the GNU General Public License as published by *\r
* the Free Software Foundation; either version 2 of the License, or *\r
#ifndef ETM_H\r
#define ETM_H\r
\r
+#include "trace.h"\r
#include "target.h"\r
#include "register.h"\r
#include "arm_jtag.h"\r
\r
-// ETM registers (V1.2 protocol)\r
+#include "armv4_5.h"\r
+\r
+/* ETM registers (V1.3 protocol) */\r
enum\r
{\r
ETM_CTRL = 0x00,\r
ETM_CONTEXTID_COMPARATOR_MASK = 0x6f, \r
};\r
\r
-\r
typedef struct etm_reg_s\r
{\r
int addr;\r
arm_jtag_t *jtag_info;\r
} etm_reg_t;\r
\r
-extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);\r
+typedef enum\r
+{\r
+ /* Port width */\r
+ ETM_PORT_4BIT = 0x00,\r
+ ETM_PORT_8BIT = 0x10,\r
+ ETM_PORT_16BIT = 0x20,\r
+ ETM_PORT_WIDTH_MASK = 0x70, \r
+ /* Port modes */\r
+ ETM_PORT_NORMAL = 0x00000,\r
+ ETM_PORT_MUXED = 0x10000,\r
+ ETM_PORT_DEMUXED = 0x20000,\r
+ ETM_PORT_MODE_MASK = 0x30000,\r
+ /* Clocking modes */\r
+ ETM_PORT_FULL_CLOCK = 0x0000,\r
+ ETM_PORT_HALF_CLOCK = 0x1000,\r
+ ETM_PORT_CLOCK_MASK = 0x1000,\r
+} etm_portmode_t;\r
+\r
+typedef enum\r
+{\r
+ /* Data trace */\r
+ ETMV1_TRACE_NONE = 0x00,\r
+ ETMV1_TRACE_DATA = 0x01,\r
+ ETMV1_TRACE_ADDR = 0x02,\r
+ ETMV1_TRACE_MASK = 0x03,\r
+ /* ContextID */\r
+ ETMV1_CONTEXTID_NONE = 0x00,\r
+ ETMV1_CONTEXTID_8 = 0x10,\r
+ ETMV1_CONTEXTID_16 = 0x20,\r
+ ETMV1_CONTEXTID_32 = 0x30,\r
+ ETMV1_CONTEXTID_MASK = 0x30,\r
+ /* Misc */\r
+ ETMV1_CYCLE_ACCURATE = 0x100\r
+} etmv1_tracemode_t;\r
+\r
+/* forward-declare ETM context */\r
+struct etm_context_s;\r
+\r
+typedef struct etm_capture_driver_s\r
+{\r
+ char *name;\r
+ int (*register_commands)(struct command_context_s *cmd_ctx);\r
+ int (*init)(struct etm_context_s *etm_ctx);\r
+ trace_status_t (*status)(struct etm_context_s *etm_ctx);\r
+ int (*read_trace)(struct etm_context_s *etm_ctx);\r
+ int (*start_capture)(struct etm_context_s *etm_ctx);\r
+ int (*stop_capture)(struct etm_context_s *etm_ctx);\r
+} etm_capture_driver_t;\r
+\r
+typedef struct etmv1_trace_data_s\r
+{\r
+ u8 pipestat; /* pipeline cycle this packet belongs to */\r
+ u16 packet; /* packet data (4, 8 or 16 bit) */\r
+ int tracesync; /* 1 if tracesync was set on this packet */\r
+} etmv1_trace_data_t;\r
+\r
+/* describe a trace context\r
+ * if support for ETMv2 or ETMv3 is to be implemented,\r
+ * this will have to be split into version independent elements\r
+ * and a version specific part\r
+ */\r
+typedef struct etm_context_s\r
+{\r
+ reg_cache_t *reg_cache; /* ETM register cache */\r
+ etm_capture_driver_t *capture_driver; /* driver used to access ETM data */\r
+ void *capture_driver_priv; /* capture driver private data */\r
+ trace_status_t capture_status; /* current state of capture run */ \r
+ etmv1_trace_data_t *trace_data; /* trace data */\r
+ u32 trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */\r
+ etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */\r
+ etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */ \r
+ armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */\r
+// trace_image_provider_t image_provider; /* source for target opcodes */\r
+ u32 pipe_index; /* current trace cycle */\r
+ u32 data_index; /* cycle holding next data packet */\r
+ u32 current_pc; /* current program counter */\r
+ u32 pc_ok; /* full PC has been acquired */\r
+ u32 last_branch; /* last branch address output */ \r
+ u32 last_ptr; /* address of the last data access */\r
+ u32 context_id; /* context ID of the code being traced */\r
+} etm_context_t;\r
+\r
+/* PIPESTAT values */\r
+typedef enum\r
+{\r
+ STAT_IE = 0x0,\r
+ STAT_ID = 0x1,\r
+ STAT_IN = 0x2,\r
+ STAT_WT = 0x3,\r
+ STAT_BE = 0x4,\r
+ STAT_BD = 0x5,\r
+ STAT_TR = 0x6,\r
+ STAT_TD = 0x7\r
+} etmv1_pipestat_t;\r
+\r
+/* branch reason values */\r
+typedef enum\r
+{\r
+ BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */\r
+ BR_ENABLE = 0x1, /* Trace has been enabled */\r
+ BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */\r
+ BR_NODEBUG = 0x3, /* ARM has exited for debug state */\r
+ BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/\r
+ BR_RSVD5 = 0x5, /* reserved */\r
+ BR_RSVD6 = 0x6, /* reserved */\r
+ BR_RSVD7 = 0x7, /* reserved */\r
+} etmv1_branch_reason_t;\r
+\r
+extern char *etmv1v1_branch_reason_strings[];\r
+\r
+extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);\r
extern int etm_read_reg(reg_t *reg);\r
extern int etm_write_reg(reg_t *reg, u32 value);\r
extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);\r
extern int etm_set_reg(reg_t *reg, u32 value);\r
extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);\r
\r
+int etm_register_commands(struct command_context_s *cmd_ctx);\r
+int etm_register_user_commands(struct command_context_s *cmd_ctx);\r
+extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);\r
+\r
+#define ERROR_ETM_INVALID_DRIVER (-1300)\r
+#define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)\r
+#define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)\r
+\r
#endif /* ETM_H */\r
Code Review / openocd.git / blobdiff