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- This speeds up dcc arm7_9 bulk write a little bit and exercises the jtag_add_dr_out...
[openocd.git] / src / target / embeddedice.c
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 6cf698161ed0ee5275fac4ebaa0998a510dda486..3b9af755716d3f2db8bd1cc3689405a49d7f6a79 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -169,11 +169,25 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
                case 6:
                        reg_list[EICE_DBG_CTRL].size = 6;
                        reg_list[EICE_DBG_STAT].size = 10;
-                       arm7_9->has_single_step = 1;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               case 7:
+                       WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 5;
                        arm7_9->has_monitor_mode = 1;
                        break;
                default:
-                       ERROR("unknown EmbeddedICE version (comms ctrl: 0x%4.4x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+                       ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+       }
+       
+       /* explicitly disable monitor mode */
+       if (arm7_9->has_monitor_mode)
+       {
+               embeddedice_read_reg(&reg_list[EICE_DBG_CTRL]);
+               jtag_execute_queue();
+               buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
+               embeddedice_set_reg_w_exec(&reg_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
        }
        
        return reg_cache;
@@ -200,12 +214,15 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        embeddedice_reg_t *ice_reg = reg->arch_info;
        u8 reg_addr = ice_reg->addr & 0x1f;
        scan_field_t fields[3];
-       
+       u8 field1_out[1];
+       u8 field2_out[1];
+
        DEBUG("%i", ice_reg->addr);
 
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(ice_reg->jtag_info, 0x2);
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
+       
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
        
        fields[0].device = ice_reg->jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -219,7 +236,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        
        fields[1].device = ice_reg->jtag_info->chain_pos;
        fields[1].num_bits = 5;
-       fields[1].out_value = malloc(1);
+       fields[1].out_value = field1_out;
        buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
        fields[1].out_mask = NULL;
        fields[1].in_value = NULL;
@@ -230,7 +247,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 
        fields[2].device = ice_reg->jtag_info->chain_pos;
        fields[2].num_bits = 1;
-       fields[2].out_value = malloc(1);
+       fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 0);
        fields[2].out_mask = NULL;
        fields[2].in_value = NULL;
@@ -242,8 +259,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        jtag_add_dr_scan(3, fields, -1);
        
        fields[0].in_value = reg->value;
-       fields[0].in_check_value = check_value;
-       fields[0].in_check_mask = check_mask;
+       jtag_set_check_value(fields+0, check_value, check_mask, NULL);
        
        /* when reading the DCC data register, leaving the address field set to
         * EICE_COMMS_DATA would read the register twice
@@ -253,12 +269,76 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        
        jtag_add_dr_scan(3, fields, -1);
 
-       free(fields[1].out_value);
-       free(fields[2].out_value);
-       
        return ERROR_OK;
 }
 
+/* receive <size> words of 32 bit from the DCC
+ * we pretend the target is always going to be fast enough
+ * (relative to the JTAG clock), so we don't need to handshake
+ */
+int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
+{
+       scan_field_t fields[3];
+       u8 field1_out[1];
+       u8 field2_out[1];
+
+       jtag_add_end_state(TAP_RTI);
+       arm_jtag_scann(jtag_info, 0x2);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       
+       fields[0].device = jtag_info->chain_pos;
+       fields[0].num_bits = 32;
+       fields[0].out_value = NULL;
+       fields[0].out_mask = NULL;
+       fields[0].in_value = NULL;
+       fields[0].in_check_value = NULL;
+       fields[0].in_check_mask = NULL;
+       fields[0].in_handler = NULL;
+       fields[0].in_handler_priv = NULL;
+       
+       fields[1].device = jtag_info->chain_pos;
+       fields[1].num_bits = 5;
+       fields[1].out_value = field1_out;
+       buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
+       fields[1].out_mask = NULL;
+       fields[1].in_value = NULL;
+       fields[1].in_check_value = NULL;
+       fields[1].in_check_mask = NULL;
+       fields[1].in_handler = NULL;
+       fields[1].in_handler_priv = NULL;
+
+       fields[2].device = jtag_info->chain_pos;
+       fields[2].num_bits = 1;
+       fields[2].out_value = field2_out;
+       buf_set_u32(fields[2].out_value, 0, 1, 0);
+       fields[2].out_mask = NULL;
+       fields[2].in_value = NULL;
+       fields[2].in_check_value = NULL;
+       fields[2].in_check_mask = NULL;
+       fields[2].in_handler = NULL;
+       fields[2].in_handler_priv = NULL;
+       
+       jtag_add_dr_scan(3, fields, -1);
+       
+       while (size > 0)
+       {
+               /* when reading the last item, set the register address to the DCC control reg,
+                * to avoid reading additional data from the DCC data reg
+                */
+               if (size == 1)
+                       buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
+               
+               fields[0].in_handler = arm_jtag_buf_to_u32;
+               fields[0].in_handler_priv = data;
+               jtag_add_dr_scan(3, fields, -1);
+               
+               data++;
+               size--;
+       }
+       
+       return jtag_execute_queue();
+}
+
 int embeddedice_read_reg(reg_t *reg)
 {
        return embeddedice_read_reg_w_check(reg, NULL, NULL);   
@@ -294,30 +374,54 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 int embeddedice_write_reg(reg_t *reg, u32 value)
 {
        embeddedice_reg_t *ice_reg = reg->arch_info;
-       u8 reg_addr = ice_reg->addr & 0x1f;
-       scan_field_t fields[3];
-       
+
        DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(ice_reg->jtag_info, 0x2);
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
        
-       fields[0].device = ice_reg->jtag_info->chain_pos;
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+
+       u8 reg_addr = ice_reg->addr & 0x1f;
+       embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
+       
+       return ERROR_OK;
+}
+
+int embeddedice_store_reg(reg_t *reg)
+{
+       return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+}
+
+/* send <size> words of 32 bit to the DCC
+ * we pretend the target is always going to be fast enough
+ * (relative to the JTAG clock), so we don't need to handshake
+ */
+int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
+{
+       scan_field_t fields[3];
+       u8 field0_out[4];
+       u8 field1_out[1];
+       u8 field2_out[1];
+
+       jtag_add_end_state(TAP_RTI);
+       arm_jtag_scann(jtag_info, 0x2);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+
+       fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
-       fields[0].out_value = malloc(4);
-       buf_set_u32(fields[0].out_value, 0, 32, value);
+       fields[0].out_value = field0_out;
        fields[0].out_mask = NULL;
        fields[0].in_value = NULL;
        fields[0].in_check_value = NULL;
        fields[0].in_check_mask = NULL;
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
-       
-       fields[1].device = ice_reg->jtag_info->chain_pos;
+
+       fields[1].device = jtag_info->chain_pos;
        fields[1].num_bits = 5;
-       fields[1].out_value = malloc(1);
-       buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
+       fields[1].out_value = field1_out;
+       buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
        fields[1].out_mask = NULL;
        fields[1].in_value = NULL;
        fields[1].in_check_value = NULL;
@@ -325,9 +429,9 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = ice_reg->jtag_info->chain_pos;
+       fields[2].device = jtag_info->chain_pos;
        fields[2].num_bits = 1;
-       fields[2].out_value = malloc(1);
+       fields[2].out_value = field2_out;
        buf_set_u32(fields[2].out_value, 0, 1, 1);
        fields[2].out_mask = NULL;
        fields[2].in_value = NULL;
@@ -335,18 +439,90 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
        fields[2].in_check_mask = NULL;
        fields[2].in_handler = NULL;
        fields[2].in_handler_priv = NULL;
-       
-       jtag_add_dr_scan(3, fields, -1);
-       
-       free(fields[0].out_value);
-       free(fields[1].out_value);
-       free(fields[2].out_value);
-       
+
+       while (size > 0)
+       {
+               buf_set_u32(fields[0].out_value, 0, 32, *data);
+               jtag_add_dr_scan(3, fields, -1);
+
+               data++;
+               size--;
+       }
+
+       /* call to jtag_execute_queue() intentionally omitted */
        return ERROR_OK;
 }
 
-int embeddedice_store_reg(reg_t *reg)
+/* wait for DCC control register R/W handshake bit to become active
+ */
+int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 {
-       return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
+       scan_field_t fields[3];
+       u8 field0_in[4];
+       u8 field1_out[1];
+       u8 field2_out[1];
+       int retval;
+       int hsact;
+       struct timeval lap;
+       struct timeval now;
+
+       if (hsbit == EICE_COMM_CTRL_WBIT)
+               hsact = 1;
+       else if (hsbit == EICE_COMM_CTRL_RBIT)
+               hsact = 0;
+       else
+               return ERROR_INVALID_ARGUMENTS;
+
+       jtag_add_end_state(TAP_RTI);
+       arm_jtag_scann(jtag_info, 0x2);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
+       fields[0].device = jtag_info->chain_pos;
+       fields[0].num_bits = 32;
+       fields[0].out_value = NULL;
+       fields[0].out_mask = NULL;
+       fields[0].in_value = field0_in;
+       fields[0].in_check_value = NULL;
+       fields[0].in_check_mask = NULL;
+       fields[0].in_handler = NULL;
+       fields[0].in_handler_priv = NULL;
+
+       fields[1].device = jtag_info->chain_pos;
+       fields[1].num_bits = 5;
+       fields[1].out_value = field1_out;
+       buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
+       fields[1].out_mask = NULL;
+       fields[1].in_value = NULL;
+       fields[1].in_check_value = NULL;
+       fields[1].in_check_mask = NULL;
+       fields[1].in_handler = NULL;
+       fields[1].in_handler_priv = NULL;
+
+       fields[2].device = jtag_info->chain_pos;
+       fields[2].num_bits = 1;
+       fields[2].out_value = field2_out;
+       buf_set_u32(fields[2].out_value, 0, 1, 0);
+       fields[2].out_mask = NULL;
+       fields[2].in_value = NULL;
+       fields[2].in_check_value = NULL;
+       fields[2].in_check_mask = NULL;
+       fields[2].in_handler = NULL;
+       fields[2].in_handler_priv = NULL;
+
+       jtag_add_dr_scan(3, fields, -1);
+       gettimeofday(&lap, NULL);
+       do
+       {
+               jtag_add_dr_scan(3, fields, -1);
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
+                       return retval;
+
+               if (buf_get_u32(field0_in, hsbit, 1) == hsact)
+                       return ERROR_OK;
+
+               gettimeofday(&now, NULL);
+       }
+       while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
+
+       return ERROR_TARGET_TIMEOUT;
+}
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