-/***************************************************************************
- * Copyright (C) 2005 by Dominic Rath *
- * Dominic.Rath@gmx.de *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "embeddedice.h"
-
-#include "armv4_5.h"
-#include "arm7_9_common.h"
-
-#include "log.h"
-#include "arm_jtag.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
-
-#include <stdlib.h>
-
-bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
-{
- {"R", 1},
- {"W", 1},
- {"reserved", 26},
- {"version", 4}
-};
-
-int embeddedice_reg_arch_info[] =
-{
- 0x0, 0x1, 0x4, 0x5,
- 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
- 0x2
-};
-
-char* embeddedice_reg_list[] =
-{
- "debug_ctrl",
- "debug_status",
-
- "comms_ctrl",
- "comms_data",
-
- "watch 0 addr value",
- "watch 0 addr mask",
- "watch 0 data value",
- "watch 0 data mask",
- "watch 0 control value",
- "watch 0 control mask",
-
- "watch 1 addr value",
- "watch 1 addr mask",
- "watch 1 data value",
- "watch 1 data mask",
- "watch 1 control value",
- "watch 1 control mask",
-
- "vector catch"
-};
-
-int embeddedice_reg_arch_type = -1;
-
-int embeddedice_get_reg(reg_t *reg);
-int embeddedice_set_reg(reg_t *reg, u32 value);
-int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
-
-int embeddedice_write_reg(reg_t *reg, u32 value);
-int embeddedice_read_reg(reg_t *reg);
-
-reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
-{
- reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
- reg_t *reg_list = NULL;
- embeddedice_reg_t *arch_info = NULL;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- int num_regs;
- int i;
- int eice_version = 0;
-
- /* register a register arch-type for EmbeddedICE registers only once */
- if (embeddedice_reg_arch_type == -1)
- embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
-
- if (arm7_9->has_vector_catch)
- num_regs = 17;
- else
- num_regs = 16;
-
- /* the actual registers are kept in two arrays */
- reg_list = calloc(num_regs, sizeof(reg_t));
- arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
-
- /* fill in values for the reg cache */
- reg_cache->name = "EmbeddedICE registers";
- reg_cache->next = NULL;
- reg_cache->reg_list = reg_list;
- reg_cache->num_regs = num_regs;
-
- /* set up registers */
- for (i = 0; i < num_regs; i++)
- {
- reg_list[i].name = embeddedice_reg_list[i];
- reg_list[i].size = 32;
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].arch_info = &arch_info[i];
- reg_list[i].arch_type = embeddedice_reg_arch_type;
- arch_info[i].addr = embeddedice_reg_arch_info[i];
- arch_info[i].jtag_info = jtag_info;
- }
-
- /* identify EmbeddedICE version by reading DCC control register */
- embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
- jtag_execute_queue();
-
- eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
-
- switch (eice_version)
- {
- case 1:
- reg_list[EICE_DBG_CTRL].size = 3;
- reg_list[EICE_DBG_STAT].size = 5;
- break;
- case 2:
- reg_list[EICE_DBG_CTRL].size = 4;
- reg_list[EICE_DBG_STAT].size = 5;
- arm7_9->has_single_step = 1;
- break;
- case 3:
- ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
- reg_list[EICE_DBG_CTRL].size = 6;
- reg_list[EICE_DBG_STAT].size = 5;
- arm7_9->has_single_step = 1;
- arm7_9->has_monitor_mode = 1;
- break;
- case 4:
- reg_list[EICE_DBG_CTRL].size = 6;
- reg_list[EICE_DBG_STAT].size = 5;
- arm7_9->has_monitor_mode = 1;
- break;
- case 5:
- reg_list[EICE_DBG_CTRL].size = 6;
- reg_list[EICE_DBG_STAT].size = 5;
- arm7_9->has_single_step = 1;
- arm7_9->has_monitor_mode = 1;
- break;
- case 6:
- reg_list[EICE_DBG_CTRL].size = 6;
- reg_list[EICE_DBG_STAT].size = 10;
- arm7_9->has_monitor_mode = 1;
- break;
- case 7:
- WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
- reg_list[EICE_DBG_CTRL].size = 6;
- reg_list[EICE_DBG_STAT].size = 5;
- arm7_9->has_monitor_mode = 1;
- break;
- default:
- ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
- }
-
- /* explicitly disable monitor mode */
- if (arm7_9->has_monitor_mode)
- {
- embeddedice_read_reg(®_list[EICE_DBG_CTRL]);
- jtag_execute_queue();
- buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
- embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
- }
-
- return reg_cache;
-}
-
-int embeddedice_get_reg(reg_t *reg)
-{
- if (embeddedice_read_reg(reg) != ERROR_OK)
- {
- ERROR("BUG: error scheduling EmbeddedICE register read");
- exit(-1);
- }
-
- if (jtag_execute_queue() != ERROR_OK)
- {
- ERROR("register read failed");
- }
-
- return ERROR_OK;
-}
-
-int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
-{
- embeddedice_reg_t *ice_reg = reg->arch_info;
- u8 reg_addr = ice_reg->addr & 0x1f;
- scan_field_t fields[3];
- u8 field1_out[1];
- u8 field2_out[1];
-
- DEBUG("%i", ice_reg->addr);
-
- jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(ice_reg->jtag_info, 0x2);
-
- arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
-
- fields[0].device = ice_reg->jtag_info->chain_pos;
- fields[0].num_bits = 32;
- fields[0].out_value = reg->value;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = ice_reg->jtag_info->chain_pos;
- fields[1].num_bits = 5;
- fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- fields[2].device = ice_reg->jtag_info->chain_pos;
- fields[2].num_bits = 1;
- fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- fields[0].in_value = reg->value;
- jtag_set_check_value(fields+0, check_value, check_mask, NULL);
-
- /* when reading the DCC data register, leaving the address field set to
- * EICE_COMMS_DATA would read the register twice
- * reading the control register is safe
- */
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- return ERROR_OK;
-}
-
-/* receive <size> words of 32 bit from the DCC
- * we pretend the target is always going to be fast enough
- * (relative to the JTAG clock), so we don't need to handshake
- */
-int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
-{
- scan_field_t fields[3];
- u8 field1_out[1];
- u8 field2_out[1];
-
- jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0x2);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
- fields[0].num_bits = 32;
- fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
- fields[1].num_bits = 5;
- fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- fields[2].device = jtag_info->chain_pos;
- fields[2].num_bits = 1;
- fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- while (size > 0)
- {
- /* when reading the last item, set the register address to the DCC control reg,
- * to avoid reading additional data from the DCC data reg
- */
- if (size == 1)
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
-
- fields[0].in_handler = arm_jtag_buf_to_u32;
- fields[0].in_handler_priv = data;
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- data++;
- size--;
- }
-
- return jtag_execute_queue();
-}
-
-int embeddedice_read_reg(reg_t *reg)
-{
- return embeddedice_read_reg_w_check(reg, NULL, NULL);
-}
-
-int embeddedice_set_reg(reg_t *reg, u32 value)
-{
- if (embeddedice_write_reg(reg, value) != ERROR_OK)
- {
- ERROR("BUG: error scheduling EmbeddedICE register write");
- exit(-1);
- }
-
- buf_set_u32(reg->value, 0, reg->size, value);
- reg->valid = 1;
- reg->dirty = 0;
-
- return ERROR_OK;
-}
-
-int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
-{
- embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
-
- if (jtag_execute_queue() != ERROR_OK)
- {
- ERROR("register write failed");
- exit(-1);
- }
- return ERROR_OK;
-}
-
-int embeddedice_write_reg(reg_t *reg, u32 value)
-{
- embeddedice_reg_t *ice_reg = reg->arch_info;
- u8 reg_addr = ice_reg->addr & 0x1f;
- scan_field_t fields[3];
- u8 field0_out[4];
- u8 field1_out[1];
- u8 field2_out[1];
-
- DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
-
- jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(ice_reg->jtag_info, 0x2);
-
- arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
-
- fields[0].device = ice_reg->jtag_info->chain_pos;
- fields[0].num_bits = 32;
- fields[0].out_value = field0_out;
- buf_set_u32(fields[0].out_value, 0, 32, value);
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = ice_reg->jtag_info->chain_pos;
- fields[1].num_bits = 5;
- fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- fields[2].device = ice_reg->jtag_info->chain_pos;
- fields[2].num_bits = 1;
- fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 1);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- return ERROR_OK;
-}
-
-int embeddedice_store_reg(reg_t *reg)
-{
- return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
-
-/* send <size> words of 32 bit to the DCC
- * we pretend the target is always going to be fast enough
- * (relative to the JTAG clock), so we don't need to handshake
- */
-int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
-{
- scan_field_t fields[3];
- u8 field0_out[4];
- u8 field1_out[1];
- u8 field2_out[1];
-
- jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0x2);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
- fields[0].num_bits = 32;
- fields[0].out_value = field0_out;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
- fields[1].num_bits = 5;
- fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- fields[2].device = jtag_info->chain_pos;
- fields[2].num_bits = 1;
- fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 1);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- while (size > 0)
- {
- buf_set_u32(fields[0].out_value, 0, 32, *data);
- jtag_add_dr_scan(3, fields, -1, NULL);
-
- data++;
- size--;
- }
-
- /* call to jtag_execute_queue() intentionally omitted */
- return ERROR_OK;
-}
-
-/* wait for DCC control register R/W handshake bit to become active
- */
-int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
-{
- scan_field_t fields[3];
- u8 field0_in[4];
- u8 field1_out[1];
- u8 field2_out[1];
- int retval;
- int hsact;
- struct timeval lap;
- struct timeval now;
-
- if (hsbit == EICE_COMM_CTRL_WBIT)
- hsact = 1;
- else if (hsbit == EICE_COMM_CTRL_RBIT)
- hsact = 0;
- else
- return ERROR_INVALID_ARGUMENTS;
-
- jtag_add_end_state(TAP_RTI);
- arm_jtag_scann(jtag_info, 0x2);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
- fields[0].num_bits = 32;
- fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
- fields[0].in_value = field0_in;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
- fields[1].num_bits = 5;
- fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- fields[2].device = jtag_info->chain_pos;
- fields[2].num_bits = 1;
- fields[2].out_value = field2_out;
- buf_set_u32(fields[2].out_value, 0, 1, 0);
- fields[2].out_mask = NULL;
- fields[2].in_value = NULL;
- fields[2].in_check_value = NULL;
- fields[2].in_check_mask = NULL;
- fields[2].in_handler = NULL;
- fields[2].in_handler_priv = NULL;
-
- jtag_add_dr_scan(3, fields, -1, NULL);
- gettimeofday(&lap, NULL);
- do
- {
- jtag_add_dr_scan(3, fields, -1, NULL);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- return retval;
-
- if (buf_get_u32(field0_in, hsbit, 1) == hsact)
- return ERROR_OK;
-
- gettimeofday(&now, NULL);
- }
- while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
-
- return ERROR_TARGET_TIMEOUT;
-}
+/***************************************************************************\r
+ * Copyright (C) 2005 by Dominic Rath *\r
+ * Dominic.Rath@gmx.de *\r
+ * *\r
+ * This program is free software; you can redistribute it and/or modify *\r
+ * it under the terms of the GNU General Public License as published by *\r
+ * the Free Software Foundation; either version 2 of the License, or *\r
+ * (at your option) any later version. *\r
+ * *\r
+ * This program is distributed in the hope that it will be useful, *\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
+ * GNU General Public License for more details. *\r
+ * *\r
+ * You should have received a copy of the GNU General Public License *\r
+ * along with this program; if not, write to the *\r
+ * Free Software Foundation, Inc., *\r
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
+ ***************************************************************************/\r
+#ifdef HAVE_CONFIG_H\r
+#include "config.h"\r
+#endif\r
+\r
+#include "embeddedice.h"\r
+\r
+#include "armv4_5.h"\r
+#include "arm7_9_common.h"\r
+\r
+#include "log.h"\r
+#include "arm_jtag.h"\r
+#include "types.h"\r
+#include "binarybuffer.h"\r
+#include "target.h"\r
+#include "register.h"\r
+#include "jtag.h"\r
+\r
+#include <stdlib.h>\r
+\r
+bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = \r
+{\r
+ {"R", 1},\r
+ {"W", 1},\r
+ {"reserved", 26},\r
+ {"version", 4}\r
+};\r
+\r
+int embeddedice_reg_arch_info[] =\r
+{\r
+ 0x0, 0x1, 0x4, 0x5,\r
+ 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,\r
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,\r
+ 0x2\r
+};\r
+\r
+char* embeddedice_reg_list[] =\r
+{\r
+ "debug_ctrl",\r
+ "debug_status",\r
+ \r
+ "comms_ctrl",\r
+ "comms_data",\r
+ \r
+ "watch 0 addr value",\r
+ "watch 0 addr mask",\r
+ "watch 0 data value",\r
+ "watch 0 data mask",\r
+ "watch 0 control value",\r
+ "watch 0 control mask",\r
+ \r
+ "watch 1 addr value",\r
+ "watch 1 addr mask",\r
+ "watch 1 data value",\r
+ "watch 1 data mask",\r
+ "watch 1 control value",\r
+ "watch 1 control mask",\r
+ \r
+ "vector catch"\r
+};\r
+\r
+int embeddedice_reg_arch_type = -1;\r
+\r
+int embeddedice_get_reg(reg_t *reg);\r
+int embeddedice_set_reg(reg_t *reg, u32 value);\r
+int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);\r
+\r
+int embeddedice_write_reg(reg_t *reg, u32 value);\r
+int embeddedice_read_reg(reg_t *reg);\r
+\r
+reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)\r
+{\r
+ reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));\r
+ reg_t *reg_list = NULL;\r
+ embeddedice_reg_t *arch_info = NULL;\r
+ arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
+ int num_regs;\r
+ int i;\r
+ int eice_version = 0;\r
+ \r
+ /* register a register arch-type for EmbeddedICE registers only once */\r
+ if (embeddedice_reg_arch_type == -1)\r
+ embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);\r
+ \r
+ if (arm7_9->has_vector_catch)\r
+ num_regs = 17;\r
+ else\r
+ num_regs = 16;\r
+ \r
+ /* the actual registers are kept in two arrays */\r
+ reg_list = calloc(num_regs, sizeof(reg_t));\r
+ arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));\r
+ \r
+ /* fill in values for the reg cache */\r
+ reg_cache->name = "EmbeddedICE registers";\r
+ reg_cache->next = NULL;\r
+ reg_cache->reg_list = reg_list;\r
+ reg_cache->num_regs = num_regs;\r
+ \r
+ /* set up registers */\r
+ for (i = 0; i < num_regs; i++)\r
+ {\r
+ reg_list[i].name = embeddedice_reg_list[i];\r
+ reg_list[i].size = 32;\r
+ reg_list[i].dirty = 0;\r
+ reg_list[i].valid = 0;\r
+ reg_list[i].bitfield_desc = NULL;\r
+ reg_list[i].num_bitfields = 0;\r
+ reg_list[i].value = calloc(1, 4);\r
+ reg_list[i].arch_info = &arch_info[i];\r
+ reg_list[i].arch_type = embeddedice_reg_arch_type;\r
+ arch_info[i].addr = embeddedice_reg_arch_info[i];\r
+ arch_info[i].jtag_info = jtag_info;\r
+ }\r
+ \r
+ /* identify EmbeddedICE version by reading DCC control register */\r
+ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);\r
+ jtag_execute_queue();\r
+ \r
+ eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);\r
+ \r
+ switch (eice_version)\r
+ {\r
+ case 1:\r
+ reg_list[EICE_DBG_CTRL].size = 3;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ break;\r
+ case 2:\r
+ reg_list[EICE_DBG_CTRL].size = 4;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ arm7_9->has_single_step = 1;\r
+ break;\r
+ case 3:\r
+ ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); \r
+ reg_list[EICE_DBG_CTRL].size = 6;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ arm7_9->has_single_step = 1;\r
+ arm7_9->has_monitor_mode = 1;\r
+ break;\r
+ case 4:\r
+ reg_list[EICE_DBG_CTRL].size = 6;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ arm7_9->has_monitor_mode = 1;\r
+ break;\r
+ case 5:\r
+ reg_list[EICE_DBG_CTRL].size = 6;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ arm7_9->has_single_step = 1;\r
+ arm7_9->has_monitor_mode = 1;\r
+ break;\r
+ case 6:\r
+ reg_list[EICE_DBG_CTRL].size = 6;\r
+ reg_list[EICE_DBG_STAT].size = 10;\r
+ arm7_9->has_monitor_mode = 1;\r
+ break;\r
+ case 7:\r
+ WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");\r
+ reg_list[EICE_DBG_CTRL].size = 6;\r
+ reg_list[EICE_DBG_STAT].size = 5;\r
+ arm7_9->has_monitor_mode = 1;\r
+ break;\r
+ default:\r
+ ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));\r
+ }\r
+ \r
+ /* explicitly disable monitor mode */\r
+ if (arm7_9->has_monitor_mode)\r
+ {\r
+ embeddedice_read_reg(®_list[EICE_DBG_CTRL]);\r
+ jtag_execute_queue();\r
+ buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);\r
+ embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);\r
+ }\r
+ \r
+ return reg_cache;\r
+}\r
+\r
+int embeddedice_get_reg(reg_t *reg)\r
+{\r
+ if (embeddedice_read_reg(reg) != ERROR_OK)\r
+ {\r
+ ERROR("BUG: error scheduling EmbeddedICE register read");\r
+ exit(-1);\r
+ }\r
+ \r
+ if (jtag_execute_queue() != ERROR_OK)\r
+ {\r
+ ERROR("register read failed");\r
+ }\r
+ \r
+ return ERROR_OK;\r
+}\r
+\r
+int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)\r
+{\r
+ embeddedice_reg_t *ice_reg = reg->arch_info;\r
+ u8 reg_addr = ice_reg->addr & 0x1f;\r
+ scan_field_t fields[3];\r
+ u8 field1_out[1];\r
+ u8 field2_out[1];\r
+\r
+ DEBUG("%i", ice_reg->addr);\r
+\r
+ jtag_add_end_state(TAP_RTI);\r
+ arm_jtag_scann(ice_reg->jtag_info, 0x2);\r
+ \r
+ arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);\r
+ \r
+ fields[0].device = ice_reg->jtag_info->chain_pos;\r
+ fields[0].num_bits = 32;\r
+ fields[0].out_value = reg->value;\r
+ fields[0].out_mask = NULL;\r
+ fields[0].in_value = NULL;\r
+ fields[0].in_check_value = NULL;\r
+ fields[0].in_check_mask = NULL;\r
+ fields[0].in_handler = NULL;\r
+ fields[0].in_handler_priv = NULL;\r
+ \r
+ fields[1].device = ice_reg->jtag_info->chain_pos;\r
+ fields[1].num_bits = 5;\r
+ fields[1].out_value = field1_out;\r
+ buf_set_u32(fields[1].out_value, 0, 5, reg_addr);\r
+ fields[1].out_mask = NULL;\r
+ fields[1].in_value = NULL;\r
+ fields[1].in_check_value = NULL;\r
+ fields[1].in_check_mask = NULL;\r
+ fields[1].in_handler = NULL;\r
+ fields[1].in_handler_priv = NULL;\r
+\r
+ fields[2].device = ice_reg->jtag_info->chain_pos;\r
+ fields[2].num_bits = 1;\r
+ fields[2].out_value = field2_out;\r
+ buf_set_u32(fields[2].out_value, 0, 1, 0);\r
+ fields[2].out_mask = NULL;\r
+ fields[2].in_value = NULL;\r
+ fields[2].in_check_value = NULL;\r
+ fields[2].in_check_mask = NULL;\r
+ fields[2].in_handler = NULL;\r
+ fields[2].in_handler_priv = NULL;\r
+ \r
+ jtag_add_dr_scan(3, fields, -1);\r
+ \r
+ fields[0].in_value = reg->value;\r
+ jtag_set_check_value(fields+0, check_value, check_mask, NULL);\r
+ \r
+ /* when reading the DCC data register, leaving the address field set to\r
+ * EICE_COMMS_DATA would read the register twice\r
+ * reading the control register is safe\r
+ */\r
+ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
+ \r
+ jtag_add_dr_scan(3, fields, -1);\r
+\r
+ return ERROR_OK;\r
+}\r
+\r
+/* receive <size> words of 32 bit from the DCC\r
+ * we pretend the target is always going to be fast enough\r
+ * (relative to the JTAG clock), so we don't need to handshake\r
+ */\r
+int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)\r
+{\r
+ scan_field_t fields[3];\r
+ u8 field1_out[1];\r
+ u8 field2_out[1];\r
+\r
+ jtag_add_end_state(TAP_RTI);\r
+ arm_jtag_scann(jtag_info, 0x2);\r
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
+ \r
+ fields[0].device = jtag_info->chain_pos;\r
+ fields[0].num_bits = 32;\r
+ fields[0].out_value = NULL;\r
+ fields[0].out_mask = NULL;\r
+ fields[0].in_value = NULL;\r
+ fields[0].in_check_value = NULL;\r
+ fields[0].in_check_mask = NULL;\r
+ fields[0].in_handler = NULL;\r
+ fields[0].in_handler_priv = NULL;\r
+ \r
+ fields[1].device = jtag_info->chain_pos;\r
+ fields[1].num_bits = 5;\r
+ fields[1].out_value = field1_out;\r
+ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);\r
+ fields[1].out_mask = NULL;\r
+ fields[1].in_value = NULL;\r
+ fields[1].in_check_value = NULL;\r
+ fields[1].in_check_mask = NULL;\r
+ fields[1].in_handler = NULL;\r
+ fields[1].in_handler_priv = NULL;\r
+\r
+ fields[2].device = jtag_info->chain_pos;\r
+ fields[2].num_bits = 1;\r
+ fields[2].out_value = field2_out;\r
+ buf_set_u32(fields[2].out_value, 0, 1, 0);\r
+ fields[2].out_mask = NULL;\r
+ fields[2].in_value = NULL;\r
+ fields[2].in_check_value = NULL;\r
+ fields[2].in_check_mask = NULL;\r
+ fields[2].in_handler = NULL;\r
+ fields[2].in_handler_priv = NULL;\r
+ \r
+ jtag_add_dr_scan(3, fields, -1);\r
+ \r
+ while (size > 0)\r
+ {\r
+ /* when reading the last item, set the register address to the DCC control reg,\r
+ * to avoid reading additional data from the DCC data reg\r
+ */\r
+ if (size == 1)\r
+ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
+ \r
+ fields[0].in_handler = arm_jtag_buf_to_u32;\r
+ fields[0].in_handler_priv = data;\r
+ jtag_add_dr_scan(3, fields, -1);\r
+ \r
+ data++;\r
+ size--;\r
+ }\r
+ \r
+ return jtag_execute_queue();\r
+}\r
+\r
+int embeddedice_read_reg(reg_t *reg)\r
+{\r
+ return embeddedice_read_reg_w_check(reg, NULL, NULL); \r
+}\r
+\r
+int embeddedice_set_reg(reg_t *reg, u32 value)\r
+{\r
+ if (embeddedice_write_reg(reg, value) != ERROR_OK)\r
+ {\r
+ ERROR("BUG: error scheduling EmbeddedICE register write");\r
+ exit(-1);\r
+ }\r
+ \r
+ buf_set_u32(reg->value, 0, reg->size, value);\r
+ reg->valid = 1;\r
+ reg->dirty = 0;\r
+ \r
+ return ERROR_OK;\r
+}\r
+\r
+int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)\r
+{\r
+ embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));\r
+ \r
+ if (jtag_execute_queue() != ERROR_OK)\r
+ {\r
+ ERROR("register write failed");\r
+ exit(-1);\r
+ }\r
+ return ERROR_OK;\r
+}\r
+\r
+int embeddedice_write_reg(reg_t *reg, u32 value)\r
+{\r
+ embeddedice_reg_t *ice_reg = reg->arch_info;\r
+ u8 reg_addr = ice_reg->addr & 0x1f;\r
+ scan_field_t fields[3];\r
+ u8 field0_out[4];\r
+ u8 field1_out[1];\r
+ u8 field2_out[1];\r
+\r
+ DEBUG("%i: 0x%8.8x", ice_reg->addr, value);\r
+ \r
+ jtag_add_end_state(TAP_RTI);\r
+ arm_jtag_scann(ice_reg->jtag_info, 0x2);\r
+ \r
+ arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);\r
+ \r
+ fields[0].device = ice_reg->jtag_info->chain_pos;\r
+ fields[0].num_bits = 32;\r
+ fields[0].out_value = field0_out;\r
+ buf_set_u32(fields[0].out_value, 0, 32, value);\r
+ fields[0].out_mask = NULL;\r
+ fields[0].in_value = NULL;\r
+ fields[0].in_check_value = NULL;\r
+ fields[0].in_check_mask = NULL;\r
+ fields[0].in_handler = NULL;\r
+ fields[0].in_handler_priv = NULL;\r
+ \r
+ fields[1].device = ice_reg->jtag_info->chain_pos;\r
+ fields[1].num_bits = 5;\r
+ fields[1].out_value = field1_out;\r
+ buf_set_u32(fields[1].out_value, 0, 5, reg_addr);\r
+ fields[1].out_mask = NULL;\r
+ fields[1].in_value = NULL;\r
+ fields[1].in_check_value = NULL;\r
+ fields[1].in_check_mask = NULL;\r
+ fields[1].in_handler = NULL;\r
+ fields[1].in_handler_priv = NULL;\r
+\r
+ fields[2].device = ice_reg->jtag_info->chain_pos;\r
+ fields[2].num_bits = 1;\r
+ fields[2].out_value = field2_out;\r
+ buf_set_u32(fields[2].out_value, 0, 1, 1);\r
+ fields[2].out_mask = NULL;\r
+ fields[2].in_value = NULL;\r
+ fields[2].in_check_value = NULL;\r
+ fields[2].in_check_mask = NULL;\r
+ fields[2].in_handler = NULL;\r
+ fields[2].in_handler_priv = NULL;\r
+ \r
+ jtag_add_dr_scan(3, fields, -1);\r
+ \r
+ return ERROR_OK;\r
+}\r
+\r
+int embeddedice_store_reg(reg_t *reg)\r
+{\r
+ return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));\r
+}\r
+\r
+/* send <size> words of 32 bit to the DCC\r
+ * we pretend the target is always going to be fast enough\r
+ * (relative to the JTAG clock), so we don't need to handshake\r
+ */\r
+int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)\r
+{\r
+ scan_field_t fields[3];\r
+ u8 field0_out[4];\r
+ u8 field1_out[1];\r
+ u8 field2_out[1];\r
+\r
+ jtag_add_end_state(TAP_RTI);\r
+ arm_jtag_scann(jtag_info, 0x2);\r
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
+\r
+ fields[0].device = jtag_info->chain_pos;\r
+ fields[0].num_bits = 32;\r
+ fields[0].out_value = field0_out;\r
+ fields[0].out_mask = NULL;\r
+ fields[0].in_value = NULL;\r
+ fields[0].in_check_value = NULL;\r
+ fields[0].in_check_mask = NULL;\r
+ fields[0].in_handler = NULL;\r
+ fields[0].in_handler_priv = NULL;\r
+\r
+ fields[1].device = jtag_info->chain_pos;\r
+ fields[1].num_bits = 5;\r
+ fields[1].out_value = field1_out;\r
+ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);\r
+ fields[1].out_mask = NULL;\r
+ fields[1].in_value = NULL;\r
+ fields[1].in_check_value = NULL;\r
+ fields[1].in_check_mask = NULL;\r
+ fields[1].in_handler = NULL;\r
+ fields[1].in_handler_priv = NULL;\r
+\r
+ fields[2].device = jtag_info->chain_pos;\r
+ fields[2].num_bits = 1;\r
+ fields[2].out_value = field2_out;\r
+ buf_set_u32(fields[2].out_value, 0, 1, 1);\r
+ fields[2].out_mask = NULL;\r
+ fields[2].in_value = NULL;\r
+ fields[2].in_check_value = NULL;\r
+ fields[2].in_check_mask = NULL;\r
+ fields[2].in_handler = NULL;\r
+ fields[2].in_handler_priv = NULL;\r
+\r
+ while (size > 0)\r
+ {\r
+ buf_set_u32(fields[0].out_value, 0, 32, *data);\r
+ jtag_add_dr_scan(3, fields, -1);\r
+\r
+ data++;\r
+ size--;\r
+ }\r
+\r
+ /* call to jtag_execute_queue() intentionally omitted */\r
+ return ERROR_OK;\r
+}\r
+\r
+/* wait for DCC control register R/W handshake bit to become active\r
+ */\r
+int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)\r
+{\r
+ scan_field_t fields[3];\r
+ u8 field0_in[4];\r
+ u8 field1_out[1];\r
+ u8 field2_out[1];\r
+ int retval;\r
+ int hsact;\r
+ struct timeval lap;\r
+ struct timeval now;\r
+\r
+ if (hsbit == EICE_COMM_CTRL_WBIT)\r
+ hsact = 1;\r
+ else if (hsbit == EICE_COMM_CTRL_RBIT)\r
+ hsact = 0;\r
+ else\r
+ return ERROR_INVALID_ARGUMENTS;\r
+\r
+ jtag_add_end_state(TAP_RTI);\r
+ arm_jtag_scann(jtag_info, 0x2);\r
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
+\r
+ fields[0].device = jtag_info->chain_pos;\r
+ fields[0].num_bits = 32;\r
+ fields[0].out_value = NULL;\r
+ fields[0].out_mask = NULL;\r
+ fields[0].in_value = field0_in;\r
+ fields[0].in_check_value = NULL;\r
+ fields[0].in_check_mask = NULL;\r
+ fields[0].in_handler = NULL;\r
+ fields[0].in_handler_priv = NULL;\r
+\r
+ fields[1].device = jtag_info->chain_pos;\r
+ fields[1].num_bits = 5;\r
+ fields[1].out_value = field1_out;\r
+ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);\r
+ fields[1].out_mask = NULL;\r
+ fields[1].in_value = NULL;\r
+ fields[1].in_check_value = NULL;\r
+ fields[1].in_check_mask = NULL;\r
+ fields[1].in_handler = NULL;\r
+ fields[1].in_handler_priv = NULL;\r
+\r
+ fields[2].device = jtag_info->chain_pos;\r
+ fields[2].num_bits = 1;\r
+ fields[2].out_value = field2_out;\r
+ buf_set_u32(fields[2].out_value, 0, 1, 0);\r
+ fields[2].out_mask = NULL;\r
+ fields[2].in_value = NULL;\r
+ fields[2].in_check_value = NULL;\r
+ fields[2].in_check_mask = NULL;\r
+ fields[2].in_handler = NULL;\r
+ fields[2].in_handler_priv = NULL;\r
+\r
+ jtag_add_dr_scan(3, fields, -1);\r
+ gettimeofday(&lap, NULL);\r
+ do\r
+ {\r
+ jtag_add_dr_scan(3, fields, -1);\r
+ if ((retval = jtag_execute_queue()) != ERROR_OK)\r
+ return retval;\r
+\r
+ if (buf_get_u32(field0_in, hsbit, 1) == hsact)\r
+ return ERROR_OK;\r
+\r
+ gettimeofday(&now, NULL);\r
+ }\r
+ while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);\r
+\r
+ return ERROR_TARGET_TIMEOUT;\r
+}\r
Code Review / openocd.git / blobdiff