#ifndef CORTEX_M3_H
#define CORTEX_M3_H
-#include "register.h"
-#include "target.h"
#include "armv7m.h"
-//#include "arm_adi_v5.h"
-extern char* cortex_m3_state_strings[];
#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
-#define DCRSR_WnR (1<<16)
+#define DCRSR_WnR (1 << 16)
#define DWT_CTRL 0xE0001000
+#define DWT_CYCCNT 0xE0001004
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
-#define DWT_CTRL 0xE0001000
-
/* DCB_DHCSR bit and field definitions */
-#define DBGKEY (0xA05F<<16)
-#define C_DEBUGEN (1<<0)
-#define C_HALT (1<<1)
-#define C_STEP (1<<2)
-#define C_MASKINTS (1<<3)
-#define S_REGRDY (1<<16)
-#define S_HALT (1<<17)
-#define S_SLEEP (1<<18)
-#define S_LOCKUP (1<<19)
-#define S_RETIRE_ST (1<<24)
-#define S_RESET_ST (1<<25)
+#define DBGKEY (0xA05F << 16)
+#define C_DEBUGEN (1 << 0)
+#define C_HALT (1 << 1)
+#define C_STEP (1 << 2)
+#define C_MASKINTS (1 << 3)
+#define S_REGRDY (1 << 16)
+#define S_HALT (1 << 17)
+#define S_SLEEP (1 << 18)
+#define S_LOCKUP (1 << 19)
+#define S_RETIRE_ST (1 << 24)
+#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1<<24)
-#define VC_HARDERR (1<<10)
-#define VC_BUSERR (1<<8)
-#define VC_CORERESET (1<<0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_INTERR (1 << 9)
+#define VC_BUSERR (1 << 8)
+#define VC_STATERR (1 << 7)
+#define VC_CHKERR (1 << 6)
+#define VC_NOCPERR (1 << 5)
+#define VC_MMERR (1 << 4)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
#define NVIC_BFAR 0xE000ED38
/* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY (0x5FA<<16)
-#define AIRCR_SYSRESETREQ (1<<2)
-#define AIRCR_VECTCLRACTIVE (1<<1)
-#define AIRCR_VECTRESET (1<<0)
+#define AIRCR_VECTKEY (0x5FA << 16)
+#define AIRCR_SYSRESETREQ (1 << 2)
+#define AIRCR_VECTCLRACTIVE (1 << 1)
+#define AIRCR_VECTRESET (1 << 0)
/* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA (1<<17)
+#define SHCSR_BUSFAULTENA (1 << 17)
/* NVIC_DFSR bits */
#define DFSR_HALTED 1
#define DFSR_BKPT 2
#define FPCR_CODE 0
#define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP (0<<30)
-#define FPCR_REPLACE_BKPT_LOW (1<<30)
-#define FPCR_REPLACE_BKPT_HIGH (2<<30)
-#define FPCR_REPLACE_BKPT_BOTH (3<<30)
+#define FPCR_REPLACE_REMAP (0 << 30)
+#define FPCR_REPLACE_BKPT_LOW (1 << 30)
+#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
+#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
-typedef struct cortex_m3_fp_comparator_s
+struct cortex_m3_fp_comparator
{
int used;
int type;
- u32 fpcr_value;
- u32 fpcr_address;
-} cortex_m3_fp_comparator_t;
+ uint32_t fpcr_value;
+ uint32_t fpcr_address;
+};
-typedef struct cortex_m3_dwt_comparator_s
+struct cortex_m3_dwt_comparator
{
int used;
- u32 comp;
- u32 mask;
- u32 function;
- u32 dwt_comparator_address;
-} cortex_m3_dwt_comparator_t;
+ uint32_t comp;
+ uint32_t mask;
+ uint32_t function;
+ uint32_t dwt_comparator_address;
+};
+
+enum cortex_m3_soft_reset_config
+{
+ CORTEX_M3_RESET_SYSRESETREQ,
+ CORTEX_M3_RESET_VECTRESET,
+};
-typedef struct cortex_m3_common_s
+struct cortex_m3_common
{
int common_magic;
- arm_jtag_t jtag_info;
-
+ struct arm_jtag jtag_info;
+
/* Context information */
- u32 dcb_dhcsr;
- u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
- u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
-
+ uint32_t dcb_dhcsr;
+ uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
+ uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
+
/* Flash Patch and Breakpoint (FPB) */
int fp_num_lit;
int fp_num_code;
int fp_code_available;
int fpb_enabled;
int auto_bp_type;
- cortex_m3_fp_comparator_t *fp_comparator_list;
-
+ struct cortex_m3_fp_comparator *fp_comparator_list;
+
/* Data Watchpoint and Trace (DWT) */
int dwt_num_comp;
int dwt_comp_available;
- cortex_m3_dwt_comparator_t *dwt_comparator_list;
-
- /* Interrupts */
- int intlinesnum;
- u32 *intsetenable;
-
- armv7m_common_t armv7m;
-// swjdp_common_t swjdp_info;
- void *arch_info;
-} cortex_m3_common_t;
-
-extern void cortex_m3_build_reg_cache(target_t *target);
-
-int cortex_m3_poll(target_t *target);
-int cortex_m3_halt(target_t *target);
-int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
-
-int cortex_m3_assert_reset(target_t *target);
-int cortex_m3_deassert_reset(target_t *target);
-int cortex_m3_soft_reset_halt(struct target_s *target);
-
-int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
-
-int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-
-//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
+ struct cortex_m3_dwt_comparator *dwt_comparator_list;
+ struct reg_cache *dwt_cache;
+
+ enum cortex_m3_soft_reset_config soft_reset_config;
+
+ struct armv7m_common armv7m;
+};
+
+static inline struct cortex_m3_common *
+target_to_cm3(struct target *target)
+{
+ return container_of(target->arch_info,
+ struct cortex_m3_common, armv7m);
+}
#endif /* CORTEX_M3_H */
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