/* forward declarations */
-static int cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-static int cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-static void cortex_m3_enable_watchpoints(struct target_s *target);
-static int cortex_m3_store_core_reg_u32(target_t *target,
+static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
+static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
+static void cortex_m3_enable_watchpoints(struct target *target);
+static int cortex_m3_store_core_reg_u32(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t value);
#ifdef ARMV7_GDB_HACKS
return retval;
}
-static int cortex_m3_write_debug_halt_mask(target_t *target,
+static int cortex_m3_write_debug_halt_mask(struct target *target,
uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
-static int cortex_m3_clear_halt(target_t *target)
+static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_single_step_core(target_t *target)
+static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_endreset_event(target_t *target)
+static int cortex_m3_endreset_event(struct target *target)
{
int i;
uint32_t dcb_demcr;
return ERROR_OK;
}
-static int cortex_m3_examine_debug_reason(target_t *target)
+static int cortex_m3_examine_debug_reason(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return ERROR_OK;
}
-static int cortex_m3_examine_exception_reason(target_t *target)
+static int cortex_m3_examine_exception_reason(struct target *target)
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
return ERROR_OK;
}
-static int cortex_m3_debug_entry(target_t *target)
+static int cortex_m3_debug_entry(struct target *target)
{
int i;
uint32_t xPSR;
return ERROR_OK;
}
-static int cortex_m3_poll(target_t *target)
+static int cortex_m3_poll(struct target *target)
{
int retval;
enum target_state prev_target_state = target->state;
return ERROR_OK;
}
-static int cortex_m3_halt(target_t *target)
+static int cortex_m3_halt(struct target *target)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
return ERROR_OK;
}
-static int cortex_m3_soft_reset_halt(struct target_s *target)
+static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static void cortex_m3_enable_breakpoints(struct target_s *target)
+static void cortex_m3_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
}
}
-static int cortex_m3_resume(struct target_s *target, int current,
+static int cortex_m3_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
}
/* int irqstepcount = 0; */
-static int cortex_m3_step(struct target_s *target, int current,
+static int cortex_m3_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return ERROR_OK;
}
-static int cortex_m3_assert_reset(target_t *target)
+static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_deassert_reset(target_t *target)
+static int cortex_m3_deassert_reset(struct target *target)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
}
static int
-cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
int fp_num = 0;
}
static int
-cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
uint32_t mask, temp;
}
static int
-cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct cortex_m3_dwt_comparator *comparator;
}
static int
-cortex_m3_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return ERROR_OK;
}
-static void cortex_m3_enable_watchpoints(struct target_s *target)
+static void cortex_m3_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
}
}
-static int cortex_m3_load_core_reg_u32(struct target_s *target,
+static int cortex_m3_load_core_reg_u32(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t * value)
{
int retval;
return ERROR_OK;
}
-static int cortex_m3_store_core_reg_u32(struct target_s *target,
+static int cortex_m3_store_core_reg_u32(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t value)
{
int retval;
return ERROR_OK;
}
-static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
+static int cortex_m3_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
return retval;
}
-static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
+static int cortex_m3_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
return retval;
}
-static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
{
return cortex_m3_write_memory(target, address, 4, count, buffer);
}
static int cortex_m3_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+ struct target *target)
{
armv7m_build_reg_cache(target);
return ERROR_OK;
*/
struct dwt_reg_state {
- struct target_s *target;
+ struct target *target;
uint32_t addr;
uint32_t value; /* scratch/cache */
};
static int dwt_reg_type = -1;
static void
-cortex_m3_dwt_addreg(struct target_s *t, struct reg *r, struct dwt_reg *d)
+cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
{
struct dwt_reg_state *state;
}
static void
-cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
+cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
{
uint32_t dwtcr;
struct reg_cache *cache;
*/
}
-static int cortex_m3_examine(struct target_s *target)
+static int cortex_m3_examine(struct target *target)
{
int retval;
uint32_t cpuid, fpcr;
return ERROR_OK;
}
-static int cortex_m3_target_request_data(target_t *target,
+static int cortex_m3_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
static int cortex_m3_handle_target_request(void *priv)
{
- target_t *target = priv;
+ struct target *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
struct armv7m_common *armv7m = target_to_armv7m(target);
return ERROR_OK;
}
-static int cortex_m3_init_arch_info(target_t *target,
+static int cortex_m3_init_arch_info(struct target *target,
struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
{
int retval;
return ERROR_OK;
}
-static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
uint32_t address;
unsigned long count = 1;
COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct swjdp_common *swjdp = &armv7m->swjdp_info;
COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
int retval;