The bitbang driver leaves the TCK 0 when in idle

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index bdb405039df0590441d3f8674494a62748c4401c..ca629cc6ff9cdbb49048ab3f9084716e9f1d32cb 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1,6 +1,7 @@
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
+ *                                                                         *
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
@@ -143,6 +144,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
        return retvalue;
 }
 
+#if 0
 /* Enable interrupts */
 int cortex_m3_cpsie(target_t *target, u32 IF)
 {
@@ -154,6 +156,7 @@ int cortex_m3_cpsid(target_t *target, u32 IF)
 {
        return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
 }
+#endif
 
 int cortex_m3_endreset_event(target_t *target)
 {
@@ -324,7 +327,6 @@ int cortex_m3_debug_entry(target_t *target)
                cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
        }
 
-
        /* Now we can load SP core registers */ 
        for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
        {
@@ -431,7 +433,7 @@ int cortex_m3_halt(target_t *target)
        if (target->state == TARGET_HALTED)
        {
                WARNING("target was already halted");
-               return ERROR_TARGET_ALREADY_HALTED;
+               return ERROR_OK;
        }
        
        if (target->state == TARGET_UNKNOWN)
@@ -638,7 +640,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
        return ERROR_OK;
 }
 
-//int irqstepcount=0;
+/* int irqstepcount=0; */
 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 {
        /* get pointers to arch-specific information */
@@ -1133,7 +1135,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                        ERROR("JTAG failure %i",retval);
                        return ERROR_JTAG_DEVICE_ERROR;
                }
-               //DEBUG("load from core reg %i  value 0x%x",num,*value);
+               /* DEBUG("load from core reg %i  value 0x%x",num,*value); */
        }
        else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
        {
@@ -1211,39 +1213,31 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+       int retval;
        
        /* sanitize arguments */
        if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
                return ERROR_INVALID_ARGUMENTS;
-
-       if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
-               return ERROR_TARGET_UNALIGNED_ACCESS;
        
-       /* Is not optimal, autoincrement of tar should be used (  ahbap_block_read and CSW_ADDRINC_SINGLE ) */
+       /* cortex_m3 handles unaligned memory access */
+               
        switch (size)
        {
                case 4:
-                       /* TODOLATER Check error return value ! */
-                       {
-                               ahbap_read_buf(swjdp, buffer, 4 * count, address);
-                       }
+                       retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
                case 2:
-                       {
-                               ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
-                       }       
+                       retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
                        break;
                case 1:
-                       {
-                               ahbap_read_buf(swjdp, buffer, count, address);
-                       }       
+                       retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
                        break;
                default:
                        ERROR("BUG: we shouldn't get here");
                        exit(-1);
        }
        
-       return ERROR_OK;
+       return retval;
 }
 
 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -1252,45 +1246,34 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+       int retval;
        
        /* sanitize arguments */
        if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
                return ERROR_INVALID_ARGUMENTS;
-
-       if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
-               return ERROR_TARGET_UNALIGNED_ACCESS;
-               
+       
        switch (size)
        {
                case 4:
-                       /* TODOLATER Check error return value ! */
-                       {
-                               ahbap_write_buf(swjdp, buffer, 4 * count, address);
-                       }
+                       retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
                        break;
                case 2:
-                       {
-                               ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
-                       }       
+                       retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
                        break;
                case 1:
-                       {
-                               ahbap_write_buf(swjdp, buffer, count, address);
-                       }       
+                       retval = ahbap_write_buf_u8(swjdp, buffer, count, address);     
                        break;
                default:
                        ERROR("BUG: we shouldn't get here");
                        exit(-1);
        }
        
-       return ERROR_OK;
+       return retval;
 }
 
 int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 {
-       cortex_m3_write_memory(target, address, 4, count, buffer);
-       
-       return ERROR_OK;
+       return cortex_m3_write_memory(target, address, 4, count, buffer);
 }
 
 void cortex_m3_build_reg_cache(target_t *target)
@@ -1371,8 +1354,12 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
        
        /* write ack back to software dcc register
         * signify we have read data */
-       dcrdr = 0;
-       ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+       if (dcrdr & (1 << 0))
+       {
+               dcrdr = 0;
+               ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+       }
+       
        return ERROR_OK;
 }
 
@@ -1412,10 +1399,11 @@ int cortex_m3_handle_target_request(void *priv)
                cortex_m3_dcc_read(swjdp, &data, &ctrl);
                
                /* check if we have data */
-               if (ctrl & (1<<0))
+               if (ctrl & (1 << 0))
                {
                        u32 request;
                        
+                       /* we assume target is quick enough */
                        request = data;
                        cortex_m3_dcc_read(swjdp, &data, &ctrl);
                        request |= (data << 8);
@@ -1462,7 +1450,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
        armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-//     armv7m->full_context = cortex_m3_full_context;
+       /* armv7m->full_context = cortex_m3_full_context; */
        
        target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
        
@@ -1475,6 +1463,7 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char
        int chain_pos;
        char *variant = NULL;
        cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t));
+       memset(cortex_m3, 0, sizeof(*cortex_m3));
 
        if (argc < 4)
        {