return retvalue;
}
+#if 0
/* Enable interrupts */
int cortex_m3_cpsie(target_t *target, u32 IF)
{
{
return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
}
+#endif
int cortex_m3_endreset_event(target_t *target)
{
cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
}
-
/* Now we can load SP core registers */
for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
{
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
- if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
- return ERROR_TARGET_UNALIGNED_ACCESS;
- /* Is not optimal, autoincrement of tar should be used ( ahbap_block_read and CSW_ADDRINC_SINGLE ) */
+ /* cortex_m3 handles unaligned memory access */
+
switch (size)
{
case 4:
- /* TODOLATER Check error return value ! */
- {
- ahbap_read_buf(swjdp, buffer, 4 * count, address);
- }
+ retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- {
- ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
- }
+ retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- {
- ahbap_read_buf(swjdp, buffer, count, address);
- }
+ retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
- return ERROR_OK;
+ return retval;
}
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
- if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
- return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
- /* TODOLATER Check error return value ! */
- {
- ahbap_write_buf(swjdp, buffer, 4 * count, address);
- }
+ retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- {
- ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
- }
+ retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- {
- ahbap_write_buf(swjdp, buffer, count, address);
- }
+ retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
- return ERROR_OK;
+ return retval;
}
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
- cortex_m3_write_memory(target, address, 4, count, buffer);
-
- return ERROR_OK;
+ return cortex_m3_write_memory(target, address, 4, count, buffer);
}
void cortex_m3_build_reg_cache(target_t *target)
int chain_pos;
char *variant = NULL;
cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t));
+ memset(cortex_m3, 0, sizeof(*cortex_m3));
if (argc < 4)
{