#include "register.h"
#include "arm_opcodes.h"
#include "arm_semihosting.h"
+#include <helper/time_support.h>
/* NOTE: most of this should work fine for the Cortex-M1 and
* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
* any longer.
*/
+/**
+ * Returns the type of a break point required by address location
+ */
+#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
+
/* forward declarations */
static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
+ int retval;
+ bool isr_timed_out = false;
if (target->state != TARGET_HALTED)
{
if (!current)
buf_set_u32(pc->value, 0, 32, address);
+ uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
- breakpoint = breakpoint_find(target,
- buf_get_u32(pc->value, 0, 32));
+ breakpoint = breakpoint_find(target, pc_value);
if (breakpoint)
cortex_m3_unset_breakpoint(target, breakpoint);
}
* instruction - as such simulate a step */
if (bkpt_inst_found == false)
{
- /* set step and clear halt */
- cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Automatic ISR masking mode off: Just step over the next instruction */
+ if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
+ {
+ cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ }
+ else
+ {
+ /* Process interrupts during stepping in a way they don't interfere
+ * debugging.
+ *
+ * Principle:
+ *
+ * Set a temporary break point at the current pc and let the core run
+ * with interrupts enabled. Pending interrupts get served and we run
+ * into the breakpoint again afterwards. Then we step over the next
+ * instruction with interrupts disabled.
+ *
+ * If the pending interrupts don't complete within time, we leave the
+ * core running. This may happen if the interrupts trigger faster
+ * than the core can process them or the handler doesn't return.
+ *
+ * If no more breakpoints are available we simply do a step with
+ * interrupts enabled.
+ *
+ */
+
+ /* Set a temporary break point */
+ retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value));
+ bool tmp_bp_set = (retval == ERROR_OK);
+
+ /* No more breakpoints left, just do a step */
+ if (!tmp_bp_set)
+ {
+ cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ }
+ else
+ {
+ /* Start the core */
+ LOG_DEBUG("Starting core to serve pending interrupts");
+ int64_t t_start = timeval_ms();
+ cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
+
+ /* Wait for pending handlers to complete or timeout */
+ do {
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ {
+ target->state = TARGET_UNKNOWN;
+ return retval;
+ }
+ isr_timed_out = ((timeval_ms() - t_start) > 500);
+ } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
+
+ /* Remove the temporary breakpoint */
+ breakpoint_remove(target, pc_value);
+
+ if (isr_timed_out)
+ {
+ LOG_DEBUG("Interrupt handlers didn't complete within time, "
+ "leaving target running");
+ }
+ else
+ {
+ /* Step over next instruction with interrupts disabled */
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
+ cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Re-enable interrupts */
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ }
+ }
+ }
}
- int retval;
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
+ if (isr_timed_out) {
+ /* Leave the core running. The user has to stop execution manually. */
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ target->state = TARGET_RUNNING;
+ return ERROR_OK;
+ }
+
LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32,
cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
enum reset_types jtag_reset_config = jtag_get_reset_config();
- /*
- * We can reset Cortex-M3 targets using just the NVIC without
- * requiring SRST, getting a SoC reset (or a core-only reset)
- * instead of a system reset.
- */
- if (!(jtag_reset_config & RESET_HAS_SRST) &&
- (cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) {
- reset_config = CORTEX_M3_RESET_VECTRESET;
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ /* allow scripts to override the reset event */
+
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
}
/* Enable debug requests */
return retval;
}
- if (reset_config == CORTEX_M3_RESET_SRST)
+ if (jtag_reset_config & RESET_HAS_SRST)
{
/* default to asserting srst */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
}
if (breakpoint->type == BKPT_HARD)
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
#ifdef ARMV7_GDB_HACKS
if (breakpoint->length != 2) {
/* XXX Hack: Replace all breakpoints with length != 2 with
#endif
}
- if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
- {
- LOG_INFO("flash patch comparator requested outside code memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
+ if (breakpoint->type == BKPT_HARD)
+ {
+ LOG_INFO("flash patch comparator requested outside code memory region");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
- {
- LOG_INFO("soft breakpoint requested in code (flash) memory region");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ if (breakpoint->type == BKPT_SOFT)
+ {
+ LOG_INFO("soft breakpoint requested in code (flash) memory region");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
}
if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
if (cortex_m3->auto_bp_type)
{
- breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT;
+ breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
}
if (breakpoint->set)
{
struct reg *r;
- LOG_ERROR("JTAG failure %i", retval);
+ LOG_ERROR("JTAG failure");
r = armv7m->core_cache->reg_list + num;
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
static int cortex_m3_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = &armv7m->dap;
}
static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
- uint32_t count, uint8_t *buffer)
+ uint32_t count, const uint8_t *buffer)
{
return cortex_m3_write_memory(target, address, 4, count, buffer);
}
/* default reset mode is to use srst if fitted
* if not it will use CORTEX_M3_RESET_VECTRESET */
- cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
armv7m->arm.dap = &armv7m->dap;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
int retval;
+ static const Jim_Nvp nvp_maskisr_modes[] = {
+ { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
+ { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF },
+ { .name = "on" , .value = CORTEX_M3_ISRMASK_ON },
+ { .name = NULL , .value = -1 },
+ };
+ const Jim_Nvp *n;
+
+
retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
if (retval != ERROR_OK)
return retval;
if (CMD_ARGC > 0)
{
- bool enable;
- COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
- uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
- uint32_t mask_off = enable ? 0 : C_MASKINTS;
- cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
+ n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
+ if (n->name == NULL)
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ cortex_m3->isrmasking_mode = n->value;
+
+
+ if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
+ {
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
+ }
+ else
+ {
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ }
}
- command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
- (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
+ n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
+ command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
return ERROR_OK;
}
cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
else if (strcmp(*CMD_ARGV, "vectreset") == 0)
cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
- else
- cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
}
switch (cortex_m3->soft_reset_config)
{
- case CORTEX_M3_RESET_SRST:
- reset_config = "srst";
- break;
-
case CORTEX_M3_RESET_SYSRESETREQ:
reset_config = "sysresetreq";
break;
.handler = handle_cortex_m3_mask_interrupts_command,
.mode = COMMAND_EXEC,
.help = "mask cortex_m3 interrupts",
- .usage = "['on'|'off']",
+ .usage = "['auto'|'on'|'off']",
},
{
.name = "vector_catch",
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