- add cortex_m3 variant luminary to fix reset issue with asserting SRST

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 803f05ce89c5e7746881cb54e53ab035f266091e..1f9674fad000590b9890896120275ae7bc3448a7 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -706,13 +706,26 @@ int cortex_m3_assert_reset(target_t *target)
                ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET );
        }
        
-       if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+       /* following hack is to handle luminary reset
+        * when srst is asserted the luminary device seesm to also clear the debug registers
+        * which does not match the armv7 debug TRM */
+               
+       if (strcmp(cortex_m3->variant, "luminary") == 0)
        {
-               jtag_add_reset(1, 1);
+               /* this causes the luminary device to reset using the watchdog */
+               ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
+               LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
        }
        else
        {
-               jtag_add_reset(0, 1);
+               if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+               {
+                       jtag_add_reset(1, 1);
+               }
+               else
+               {
+                       jtag_add_reset(0, 1);
+               }
        }
        
        target->state = TARGET_RESET;
@@ -1438,6 +1451,15 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
        armv7m->pre_restore_context = NULL;
        armv7m->post_restore_context = NULL;
        
+       if (variant)
+       {
+               cortex_m3->variant = strdup(variant);
+       }
+       else
+       {
+               cortex_m3->variant = strdup("");
+       }
+       
        armv7m_init_arch_info(target, armv7m);  
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;