#define ITM_LAR_KEY 0xC5ACCE55
#define CPUID 0xE000ED00
+
+#define ARM_CPUID_PARTNO_MASK 0xFFF0
+
+#define CORTEX_M23_PARTNO 0xD200
+#define CORTEX_M33_PARTNO 0xD210
+
/* Debug Control Block */
#define DCB_DHCSR 0xE000EDF0
#define DCB_DCRSR 0xE000EDF4
#define DWT_COMP0 0xE0001020
#define DWT_MASK0 0xE0001024
#define DWT_FUNCTION0 0xE0001028
+#define DWT_DEVARCH 0xE0001FBC
+
+#define DWT_DEVARCH_ARMV8M 0x101A02
#define FP_CTRL 0xE0002000
#define FP_REMAP 0xE0002004
#define DFSR_BKPT 2
#define DFSR_DWTTRAP 4
#define DFSR_VCATCH 8
+#define DFSR_EXTERNAL 16
#define FPCR_CODE 0
#define FPCR_LITERAL 1
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
struct cortex_m_fp_comparator {
- int used;
+ bool used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
struct cortex_m_dwt_comparator {
- int used;
+ bool used;
uint32_t comp;
uint32_t mask;
uint32_t function;
CORTEX_M_ISRMASK_AUTO,
CORTEX_M_ISRMASK_OFF,
CORTEX_M_ISRMASK_ON,
+ CORTEX_M_ISRMASK_STEPONLY,
};
struct cortex_m_common {
/* Flash Patch and Breakpoint (FPB) */
int fp_num_lit;
int fp_num_code;
- int fp_code_available;
int fp_rev;
- int fpb_enabled;
+ bool fpb_enabled;
struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
int dwt_num_comp;
int dwt_comp_available;
+ uint32_t dwt_devarch;
struct cortex_m_dwt_comparator *dwt_comparator_list;
struct reg_cache *dwt_cache;
enum cortex_m_soft_reset_config soft_reset_config;
+ bool vectreset_supported;
enum cortex_m_isrmasking_mode isrmasking_mode;
struct armv7m_common armv7m;
int apsel;
+
+ /* Whether this target has the erratum that makes C_MASKINTS not apply to
+ * already pending interrupts */
+ bool maskints_erratum;
};
static inline struct cortex_m_common *