cortex_m: add detection of Cortex M35P and M55

[openocd.git] / src / target / cortex_m.h

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index b375d1111d308c3c577e86ee5c1b0cb55e53c1cd..415a6c22f301d001403c92c0f765e04fb42783ac 100644 (file)
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -26,6 +26,7 @@
 #define OPENOCD_TARGET_CORTEX_M_H
 
 #include "armv7m.h"
+#include "helper/bits.h"
 
 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
 
@@ -38,13 +39,22 @@
 #define ITM_LAR_KEY    0xC5ACCE55
 
 #define CPUID          0xE000ED00
+
+#define ARM_CPUID_PARTNO_MASK  0xFFF0
+
+#define CORTEX_M23_PARTNO      0xD200
+#define CORTEX_M33_PARTNO      0xD210
+#define CORTEX_M35P_PARTNO     0xD310
+#define CORTEX_M55_PARTNO      0xD220
+
 /* Debug Control Block */
 #define DCB_DHCSR      0xE000EDF0
 #define DCB_DCRSR      0xE000EDF4
 #define DCB_DCRDR      0xE000EDF8
 #define DCB_DEMCR      0xE000EDFC
+#define DCB_DSCSR      0xE000EE08
 
-#define DCRSR_WnR      (1 << 16)
+#define DCRSR_WnR      BIT(16)
 
 #define DWT_CTRL       0xE0001000
 #define DWT_CYCCNT     0xE0001004
@@ -52,6 +62,9 @@
 #define DWT_COMP0      0xE0001020
 #define DWT_MASK0      0xE0001024
 #define DWT_FUNCTION0  0xE0001028
+#define DWT_DEVARCH            0xE0001FBC
+
+#define DWT_DEVARCH_ARMV8M     0x101A02
 
 #define FP_CTRL                0xE0002000
 #define FP_REMAP       0xE0002004
@@ -77,30 +90,37 @@
 #define TPIU_FFCR      0xE0040304
 #define TPIU_FSCR      0xE0040308
 
+/* Maximum SWO prescaler value. */
+#define TPIU_ACPR_MAX_SWOSCALER        0x1fff
+
 /* DCB_DHCSR bit and field definitions */
-#define DBGKEY         (0xA05F << 16)
-#define C_DEBUGEN      (1 << 0)
-#define C_HALT         (1 << 1)
-#define C_STEP         (1 << 2)
-#define C_MASKINTS     (1 << 3)
-#define S_REGRDY       (1 << 16)
-#define S_HALT         (1 << 17)
-#define S_SLEEP                (1 << 18)
-#define S_LOCKUP       (1 << 19)
-#define S_RETIRE_ST    (1 << 24)
-#define S_RESET_ST     (1 << 25)
+#define DBGKEY         (0xA05Ful << 16)
+#define C_DEBUGEN      BIT(0)
+#define C_HALT         BIT(1)
+#define C_STEP         BIT(2)
+#define C_MASKINTS     BIT(3)
+#define S_REGRDY       BIT(16)
+#define S_HALT         BIT(17)
+#define S_SLEEP                BIT(18)
+#define S_LOCKUP       BIT(19)
+#define S_RETIRE_ST    BIT(24)
+#define S_RESET_ST     BIT(25)
 
 /* DCB_DEMCR bit and field definitions */
-#define TRCENA                 (1 << 24)
-#define VC_HARDERR             (1 << 10)
-#define VC_INTERR              (1 << 9)
-#define VC_BUSERR              (1 << 8)
-#define VC_STATERR             (1 << 7)
-#define VC_CHKERR              (1 << 6)
-#define VC_NOCPERR             (1 << 5)
-#define VC_MMERR               (1 << 4)
-#define VC_CORERESET   (1 << 0)
-
+#define TRCENA                 BIT(24)
+#define VC_HARDERR             BIT(10)
+#define VC_INTERR              BIT(9)
+#define VC_BUSERR              BIT(8)
+#define VC_STATERR             BIT(7)
+#define VC_CHKERR              BIT(6)
+#define VC_NOCPERR             BIT(5)
+#define VC_MMERR               BIT(4)
+#define VC_CORERESET   BIT(0)
+
+/* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDS              BIT(16)
+
+/* NVIC registers */
 #define NVIC_ICTR              0xE000E004
 #define NVIC_ISE0              0xE000E100
 #define NVIC_ICSR              0xE000ED04
@@ -114,26 +134,29 @@
 #define NVIC_DFSR              0xE000ED30
 #define NVIC_MMFAR             0xE000ED34
 #define NVIC_BFAR              0xE000ED38
+#define NVIC_SFSR              0xE000EDE4
+#define NVIC_SFAR              0xE000EDE8
 
 /* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY          (0x5FA << 16)
-#define AIRCR_SYSRESETREQ      (1 << 2)
-#define AIRCR_VECTCLRACTIVE    (1 << 1)
-#define AIRCR_VECTRESET                (1 << 0)
+#define AIRCR_VECTKEY          (0x5FAul << 16)
+#define AIRCR_SYSRESETREQ      BIT(2)
+#define AIRCR_VECTCLRACTIVE    BIT(1)
+#define AIRCR_VECTRESET                BIT(0)
 /* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA      (1 << 17)
+#define SHCSR_BUSFAULTENA      BIT(17)
 /* NVIC_DFSR bits */
 #define DFSR_HALTED                    1
 #define DFSR_BKPT                      2
 #define DFSR_DWTTRAP           4
 #define DFSR_VCATCH                    8
+#define DFSR_EXTERNAL          16
 
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP  (0 << 30)
-#define FPCR_REPLACE_BKPT_LOW  (1 << 30)
-#define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
-#define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
+#define FPCR_REPLACE_REMAP  (0ul << 30)
+#define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
+#define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
+#define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 
 struct cortex_m_fp_comparator {
        bool used;
@@ -159,6 +182,7 @@ enum cortex_m_isrmasking_mode {
        CORTEX_M_ISRMASK_AUTO,
        CORTEX_M_ISRMASK_OFF,
        CORTEX_M_ISRMASK_ON,
+       CORTEX_M_ISRMASK_STEPONLY,
 };
 
 struct cortex_m_common {
@@ -172,7 +196,6 @@ struct cortex_m_common {
        /* Flash Patch and Breakpoint (FPB) */
        int fp_num_lit;
        int fp_num_code;
-       int fp_code_available;
        int fp_rev;
        bool fpb_enabled;
        struct cortex_m_fp_comparator *fp_comparator_list;
@@ -180,6 +203,7 @@ struct cortex_m_common {
        /* Data Watchpoint and Trace (DWT) */
        int dwt_num_comp;
        int dwt_comp_available;
+       uint32_t dwt_devarch;
        struct cortex_m_dwt_comparator *dwt_comparator_list;
        struct reg_cache *dwt_cache;
 
@@ -191,6 +215,10 @@ struct cortex_m_common {
        struct armv7m_common armv7m;
 
        int apsel;
+
+       /* Whether this target has the erratum that makes C_MASKINTS not apply to
+        * already pending interrupts */
+       bool maskints_erratum;
 };
 
 static inline struct cortex_m_common *