* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
* *
* *
* Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
- r = arm->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
-#ifdef ARMV7_GDB_HACKS
- /* FIXME this breaks on scan chains with more than one Cortex-M3.
- * Instead, each CM3 should have its own dummy value...
- */
- /* copy real xpsr reg for gdb, setting thumb bit */
- buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
- buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
- armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
- armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
-#endif
-
/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00) {
r->dirty = r->valid;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
+ /* soft_reset_halt is deprecated on cortex_m as the same functionality
+ * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
+ * As this reset only used VC_CORERESET it would only ever reset the cortex_m
+ * core, not the peripherals */
+ LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
+
/* Enter debug state on reset; restore DEMCR in endreset_event() */
retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
r->valid = true;
/* Make sure we are in Thumb mode */
- r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
+ r = armv7m->arm.cpsr;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;
bool srst_asserted = false;
- if (jtag_reset_config & RESET_SRST_NO_GATING) {
+ if ((jtag_reset_config & RESET_HAS_SRST) &&
+ (jtag_reset_config & RESET_SRST_NO_GATING)) {
adapter_assert_reset();
srst_asserted = true;
}
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+ LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
? "SYSRESETREQ" : "VECTRESET");
if (reset_config == CORTEX_M3_RESET_VECTRESET) {
- LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
+ LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
"handler to reset any peripherals or configure hardware srst support.");
}
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- if (cortex_m3->auto_bp_type) {
+ if (cortex_m3->auto_bp_type)
breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-#ifdef ARMV7_GDB_HACKS
- if (breakpoint->length != 2) {
- /* XXX Hack: Replace all breakpoints with length != 2 with
- * a hardware breakpoint. */
- breakpoint->type = BKPT_HARD;
- breakpoint->length = 2;
- }
-#endif
- }
if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
if (breakpoint->type == BKPT_HARD) {
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
-#ifdef ARMV7_GDB_HACKS
- /* If the LR register is being modified, make sure it will put us
- * in "thumb" mode, or an INVSTATE exception will occur. This is a
- * hack to deal with the fact that gdb will sometimes "forge"
- * return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR = 0.)
- * Valid exception return codes have bit 0 set too.
- */
- if (num == ARMV7M_R14)
- value |= 0x01;
-#endif
-
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
* Selector values for R0..R15, xPSR, MSP, and PSP.
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
- int retval = ERROR_COMMAND_SYNTAX_ERROR;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- /* cortex_m3 handles unaligned memory access */
- if (count && buffer) {
- switch (size) {
- case 4:
- retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address, true);
- break;
- case 2:
- retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
- break;
- }
- }
-
- return retval;
+ return mem_ap_read(swjdp, buffer, size, count, address, true);
}
static int cortex_m3_write_memory(struct target *target, uint32_t address,
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = armv7m->arm.dap;
- int retval = ERROR_COMMAND_SYNTAX_ERROR;
if (armv7m->arm.is_armv6m) {
/* armv6m does not handle unaligned memory access */
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- if (count && buffer) {
- switch (size) {
- case 4:
- retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address, true);
- break;
- case 2:
- retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
- break;
- }
- }
-
- return retval;
+ return mem_ap_write(swjdp, buffer, size, count, address, true);
}
static int cortex_m3_init_target(struct command_context *cmd_ctx,
uint16_t dcrdr;
int retval;
- mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
* signify we have read data */
if (dcrdr & (1 << 0)) {
dcrdr = 0;
- retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
+ retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
}
struct cortex_m3_common *cm3)
{
if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not a Cortex-M3");
+ command_print(cmd_ctx, "target is not a Cortex-M");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
- command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
+ command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
return ERROR_OK;
}
break;
}
- command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
+ command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
return ERROR_OK;
}
.name = "maskisr",
.handler = handle_cortex_m3_mask_interrupts_command,
.mode = COMMAND_EXEC,
- .help = "mask cortex_m3 interrupts",
+ .help = "mask cortex_m interrupts",
.usage = "['auto'|'on'|'off']",
},
{
.chain = armv7m_command_handlers,
},
{
- .name = "cortex_m3",
+ .name = "cortex_m",
.mode = COMMAND_EXEC,
- .help = "Cortex-M3 command group",
+ .help = "Cortex-M command group",
.usage = "",
.chain = cortex_m3_exec_command_handlers,
},
};
struct target_type cortexm3_target = {
- .name = "cortex_m3",
+ .name = "cortex_m",
+ .deprecated_name = "cortex_m3",
.poll = cortex_m3_poll,
.arch_state = armv7m_arch_state,
Code Review / openocd.git / blobdiff