cortex_m: add detection of Cortex M35P and M55

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 5ea928a323989138fc137d363bf0de91cb0cf2f7..e52332dd620dfdfcc32185dc561a4f96dd3805bf 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -445,6 +445,14 @@ static int cortex_m_examine_exception_reason(struct target *target)
                        if (retval != ERROR_OK)
                                return retval;
                        break;
+               case 7: /* Secure Fault */
+                       retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       break;
                case 11:        /* SVCall */
                        break;
                case 12:        /* Debug Monitor */
@@ -494,6 +502,18 @@ static int cortex_m_debug_entry(struct target *target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* examine PE security state */
+       bool secure_state = false;
+       if (armv7m->arm.is_armv8m) {
+               uint32_t dscsr;
+
+               retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
+               if (retval != ERROR_OK)
+                       return retval;
+
+               secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
+       }
+
        /* Examine target state and mode
         * First load register accessible through core debug port */
        int num_regs = arm->core_cache->num_regs;
@@ -540,9 +560,10 @@ static int cortex_m_debug_entry(struct target *target)
        if (armv7m->exception_number)
                cortex_m_examine_exception_reason(target);
 
-       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
+       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
                arm_mode_name(arm->core_mode),
                buf_get_u32(arm->pc->value, 0, 32),
+               secure_state ? "Secure" : "Non-Secure",
                target_state_name(target));
 
        if (armv7m->post_debug_entry) {
@@ -2148,16 +2169,24 @@ int cortex_m_examine(struct target *target)
                /* Get CPU Type */
                i = (cpuid >> 4) & 0xf;
 
+               /* Check if it is an ARMv8-M core */
+               armv7m->arm.is_armv8m = true;
+
                switch (cpuid & ARM_CPUID_PARTNO_MASK) {
                        case CORTEX_M23_PARTNO:
                                i = 23;
                                break;
-
                        case CORTEX_M33_PARTNO:
                                i = 33;
                                break;
-
+                       case CORTEX_M35P_PARTNO:
+                               i = 35;
+                               break;
+                       case CORTEX_M55_PARTNO:
+                               i = 55;
+                               break;
                        default:
+                               armv7m->arm.is_armv8m = false;
                                break;
                }
 
@@ -2188,7 +2217,7 @@ int cortex_m_examine(struct target *target)
                                LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
                                armv7m->fp_feature = FPv4_SP;
                        }
-               } else if (i == 7 || i == 33) {
+               } else if (i == 7 || i == 33 || i == 35 || i == 55) {
                        target_read_u32(target, MVFR0, &mvfr0);
                        target_read_u32(target, MVFR1, &mvfr1);