Remove FSF address from GPL notices

[openocd.git] / src / target / cortex_a.h

diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index 17e44e210578de9c764d3f9e929c268ee1bed304..e6e9e97735fc76bb512412d21e1ebebbbab63e29 100644 (file)
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -22,30 +22,48 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef CORTEX_A8_H
-#define CORTEX_A8_H
+
+#ifndef CORTEX_A_H
+#define CORTEX_A_H
 
 #include "armv7a.h"
 
-#define CORTEX_A8_COMMON_MAGIC 0x411fc082
+#define CORTEX_A_COMMON_MAGIC 0x411fc082
+#define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
+
+#define CORTEX_A5_PARTNUM 0xc05
+#define CORTEX_A7_PARTNUM 0xc07
+#define CORTEX_A8_PARTNUM 0xc08
+#define CORTEX_A9_PARTNUM 0xc09
+#define CORTEX_A15_PARTNUM 0xc0f
+#define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
+#define CORTEX_A_MIDR_PARTNUM_SHIFT 4
 
 #define CPUDBG_CPUID   0xD00
 #define CPUDBG_CTYPR   0xD04
 #define CPUDBG_TTYPR   0xD0C
 #define CPUDBG_LOCKACCESS 0xFB0
 #define CPUDBG_LOCKSTATUS 0xFB4
+#define CPUDBG_OSLAR_LK_MASK (1 << 1)
 
 #define BRP_NORMAL 0
 #define BRP_CONTEXT 1
 
-#define CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+#define CORTEX_A_PADDRDBG_CPU_SHIFT 13
 
-struct cortex_a8_brp
-{
+enum cortex_a_isrmasking_mode {
+       CORTEX_A_ISRMASK_OFF,
+       CORTEX_A_ISRMASK_ON,
+};
+
+enum cortex_a_dacrfixup_mode {
+       CORTEX_A_DACRFIXUP_OFF,
+       CORTEX_A_DACRFIXUP_ON
+};
+
+struct cortex_a_brp {
        int used;
        int type;
        uint32_t value;
@@ -53,10 +71,8 @@ struct cortex_a8_brp
        uint8_t BRPn;
 };
 
-struct cortex_a8_common
-{
+struct cortex_a_common {
        int common_magic;
-       struct arm_jtag jtag_info;
 
        /* Context information */
        uint32_t cpudbg_dscr;
@@ -65,27 +81,37 @@ struct cortex_a8_common
        uint32_t cp15_control_reg;
        /* latest cp15 register value written and cpsr processor mode */
        uint32_t cp15_control_reg_curr;
-    enum arm_mode curr_mode;
-
+       /* auxiliary control reg */
+       uint32_t cp15_aux_control_reg;
+       /* DACR */
+       uint32_t cp15_dacr_reg;
+       enum arm_mode curr_mode;
 
        /* Breakpoint register pairs */
        int brp_num_context;
        int brp_num;
        int brp_num_available;
-       struct cortex_a8_brp *brp_list;
+       struct cortex_a_brp *brp_list;
 
-       /* Use cortex_a8_read_regs_through_mem for fast register reads */
+       /* Use cortex_a_read_regs_through_mem for fast register reads */
        int fast_reg_read;
 
+       uint32_t cpuid;
+       uint32_t ctypr;
+       uint32_t ttypr;
+       uint32_t didr;
+
+       enum cortex_a_isrmasking_mode isrmasking_mode;
+       enum cortex_a_dacrfixup_mode dacrfixup_mode;
+
        struct armv7a_common armv7a_common;
 
 };
 
-static inline struct cortex_a8_common *
-target_to_cortex_a8(struct target *target)
+static inline struct cortex_a_common *
+target_to_cortex_a(struct target *target)
 {
-       return container_of(target->arch_info, struct cortex_a8_common,
-                       armv7a_common.armv4_5_common);
+       return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
 }
 
-#endif /* CORTEX_A8_H */
+#endif /* CORTEX_A_H */