#include "arm.h"
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
-#include "arm_dpm.h"
+#include "armv8_dpm.h"
+#include "arm_cti.h"
enum {
- ARMV8_R0,
+ ARMV8_R0 = 0,
ARMV8_R1,
ARMV8_R2,
ARMV8_R3,
ARMV8_R28,
ARMV8_R29,
ARMV8_R30,
- ARMV8_R31,
+ ARMV8_SP = 31,
ARMV8_PC = 32,
ARMV8_xPSR = 33,
+ ARMV8_V0 = 34,
+ ARMV8_V1,
+ ARMV8_V2,
+ ARMV8_V3,
+ ARMV8_V4,
+ ARMV8_V5,
+ ARMV8_V6,
+ ARMV8_V7,
+ ARMV8_V8,
+ ARMV8_V9,
+ ARMV8_V10,
+ ARMV8_V11,
+ ARMV8_V12,
+ ARMV8_V13,
+ ARMV8_V14,
+ ARMV8_V15,
+ ARMV8_V16,
+ ARMV8_V17,
+ ARMV8_V18,
+ ARMV8_V19,
+ ARMV8_V20,
+ ARMV8_V21,
+ ARMV8_V22,
+ ARMV8_V23,
+ ARMV8_V24,
+ ARMV8_V25,
+ ARMV8_V26,
+ ARMV8_V27,
+ ARMV8_V28,
+ ARMV8_V29,
+ ARMV8_V30,
+ ARMV8_V31,
+ ARMV8_FPSR,
+ ARMV8_FPCR,
+
+ ARMV8_ELR_EL1 = 68,
+ ARMV8_ESR_EL1 = 69,
+ ARMV8_SPSR_EL1 = 70,
+
+ ARMV8_ELR_EL2 = 71,
+ ARMV8_ESR_EL2 = 72,
+ ARMV8_SPSR_EL2 = 73,
+
+ ARMV8_ELR_EL3 = 74,
+ ARMV8_ESR_EL3 = 75,
+ ARMV8_SPSR_EL3 = 76,
+
ARMV8_LAST_REG,
};
+enum run_control_op {
+ ARMV8_RUNCONTROL_UNKNOWN = 0,
+ ARMV8_RUNCONTROL_RESUME = 1,
+ ARMV8_RUNCONTROL_HALT = 2,
+ ARMV8_RUNCONTROL_STEP = 3,
+};
#define ARMV8_COMMON_MAGIC 0x0A450AAA
uint32_t way_shift;
};
-struct armv8_cache_common {
- int ctype;
+/* information about one architecture cache at any level */
+struct armv8_arch_cache {
+ int ctype; /* cache type, CLIDR encoding */
struct armv8_cachesize d_u_size; /* data cache */
struct armv8_cachesize i_size; /* instruction cache */
+};
+
+struct armv8_cache_common {
+ int info;
+ int loc;
+ uint32_t iminline;
+ uint32_t dminline;
+ struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
int i_cache_enabled;
int d_u_cache_enabled;
+
/* l2 external unified cache if some */
void *l2_cache;
int (*flush_all_data_cache)(struct target *target);
- int (*display_cache_info)(struct command_context *cmd_ctx,
+ int (*display_cache_info)(struct command_invocation *cmd,
struct armv8_cache_common *armv8_cache);
};
struct armv8_mmu_common {
/* following field mmu working way */
int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
- uint32_t ttbr0_mask;/* masked to be used */
- uint32_t os_border;
+ uint64_t ttbr0_mask;/* masked to be used */
+
+ uint32_t ttbcr; /* cache for ttbcr register */
+ uint32_t ttbr_mask[2];
+ uint32_t ttbr_range[2];
int (*read_physical_memory)(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer);
struct arm_dpm dpm;
uint32_t debug_base;
struct adiv5_ap *debug_ap;
- struct adiv5_ap *memory_ap;
- bool memory_ap_available;
+
+ const uint32_t *opcodes;
+
/* mdir */
uint8_t multi_processor_system;
uint8_t cluster_id;
uint8_t cpu_id;
- bool is_armv7r;
- /* cache specific to V7 Memory Management Unit compatible with v4_5*/
+ /* armv8 aarch64 need below information for page translation */
+ uint8_t va_size;
+ uint8_t pa_size;
+ uint32_t page_size;
+ uint64_t ttbr_base;
+
struct armv8_mmu_common armv8_mmu;
+ struct arm_cti *cti;
+
+ /* last run-control command issued to this target (resume, halt, step) */
+ enum run_control_op last_run_control_op;
+
/* Direct processor core register read and writes */
- int (*load_core_reg_u64)(struct target *target, uint32_t num, uint64_t *value);
- int (*store_core_reg_u64)(struct target *target, uint32_t num, uint64_t value);
+ int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
+ int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
+
+ /* SIMD/FPU registers read/write interface */
+ int (*read_reg_u128)(struct armv8_common *armv8, int num,
+ uint64_t *lvalue, uint64_t *hvalue);
+ int (*write_reg_u128)(struct armv8_common *armv8, int num,
+ uint64_t lvalue, uint64_t hvalue);
int (*examine_debug_reason)(struct target *target);
int (*post_debug_entry)(struct target *target);
return container_of(target->arch_info, struct armv8_common, arm);
}
+static inline bool is_armv8(struct armv8_common *armv8)
+{
+ return armv8->common_magic == ARMV8_COMMON_MAGIC;
+}
+
/* register offsets from armv8.debug_base */
+#define CPUV8_DBG_MAINID0 0xD00
+#define CPUV8_DBG_CPUFEATURE0 0xD20
+#define CPUV8_DBG_DBGFEATURE0 0xD28
+#define CPUV8_DBG_MEMFEATURE0 0xD38
+
+#define CPUV8_DBG_LOCKACCESS 0xFB0
+#define CPUV8_DBG_LOCKSTATUS 0xFB4
+
+#define CPUV8_DBG_EDESR 0x20
+#define CPUV8_DBG_EDECR 0x24
+#define CPUV8_DBG_WFAR0 0x30
+#define CPUV8_DBG_WFAR1 0x34
+#define CPUV8_DBG_DSCR 0x088
+#define CPUV8_DBG_DRCR 0x090
+#define CPUV8_DBG_ECCR 0x098
+#define CPUV8_DBG_PRCR 0x310
+#define CPUV8_DBG_PRSR 0x314
-#define CPUDBG_WFAR 0x018
-/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
-#define CPUDBG_DSCR 0x088
-#define CPUDBG_DRCR 0x090
-#define CPUDBG_PRCR 0x310
-#define CPUDBG_PRSR 0x314
+#define CPUV8_DBG_DTRRX 0x080
+#define CPUV8_DBG_ITR 0x084
+#define CPUV8_DBG_SCR 0x088
+#define CPUV8_DBG_DTRTX 0x08c
-#define CPUDBG_DTRRX 0x080
-#define CPUDBG_ITR 0x084
-#define CPUDBG_DTRTX 0x08c
+#define CPUV8_DBG_BVR_BASE 0x400
+#define CPUV8_DBG_BCR_BASE 0x408
+#define CPUV8_DBG_WVR_BASE 0x800
+#define CPUV8_DBG_WCR_BASE 0x808
+#define CPUV8_DBG_VCR 0x01C
-#define CPUDBG_BVR_BASE 0x400
-#define CPUDBG_BCR_BASE 0x408
-#define CPUDBG_WVR_BASE 0x180
-#define CPUDBG_WCR_BASE 0x1C0
-#define CPUDBG_VCR 0x01C
+#define CPUV8_DBG_OSLAR 0x300
-#define CPUDBG_OSLAR 0x300
-#define CPUDBG_OSLSR 0x304
-#define CPUDBG_OSSRR 0x308
-#define CPUDBG_ECR 0x024
+#define CPUV8_DBG_AUTHSTATUS 0xFB8
-#define CPUDBG_DSCCR 0x028
+#define PAGE_SIZE_4KB 0x1000
+#define PAGE_SIZE_4KB_LEVEL0_BITS 39
+#define PAGE_SIZE_4KB_LEVEL1_BITS 30
+#define PAGE_SIZE_4KB_LEVEL2_BITS 21
+#define PAGE_SIZE_4KB_LEVEL3_BITS 12
-#define CPUDBG_AUTHSTATUS 0xFB8
+#define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
+#define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
+#define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
+#define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
+
+#define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
int armv8_arch_state(struct target *target);
-int armv8_identify_cache(struct target *target);
+int armv8_read_mpidr(struct armv8_common *armv8);
+int armv8_identify_cache(struct armv8_common *armv8);
int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
target_addr_t *val, int meminfo);
-int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
+int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
struct armv8_cache_common *armv8_cache);
+void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
+
+static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
+{
+ switch (core_mode) {
+ /* Aarch32 modes */
+ case ARM_MODE_USR:
+ return 0;
+ case ARM_MODE_SVC:
+ case ARM_MODE_ABT: /* FIXME: EL3? */
+ case ARM_MODE_IRQ: /* FIXME: EL3? */
+ case ARM_MODE_FIQ: /* FIXME: EL3? */
+ case ARM_MODE_UND: /* FIXME: EL3? */
+ case ARM_MODE_SYS: /* FIXME: EL3? */
+ return 1;
+ /* case ARM_MODE_HYP:
+ * return 2;
+ */
+ case ARM_MODE_MON:
+ return 3;
+ /* all Aarch64 modes */
+ default:
+ return (core_mode >> 2) & 3;
+ }
+}
+
+void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
+
+extern void armv8_free_reg_cache(struct target *target);
+
extern const struct command_registration armv8_command_handlers[];
-#endif
+#endif /* OPENOCD_TARGET_ARMV8_H */
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