#include "target_type.h"
static const char * const armv8_state_strings[] = {
- "ARM", "Thumb", "Jazelle", "ThumbEE", "ARM64",
+ "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
};
static const struct {
} armv8_mode_data[] = {
/* These special modes are currently only supported
* by ARMv6M and ARMv7M profiles */
+ {
+ .name = "USR",
+ .psr = ARM_MODE_USR,
+ },
+ {
+ .name = "FIQ",
+ .psr = ARM_MODE_FIQ,
+ },
+ {
+ .name = "IRQ",
+ .psr = ARM_MODE_IRQ,
+ },
+ {
+ .name = "SVC",
+ .psr = ARM_MODE_SVC,
+ },
+ {
+ .name = "MON",
+ .psr = ARM_MODE_MON,
+ },
+ {
+ .name = "ABT",
+ .psr = ARM_MODE_ABT,
+ },
{
.name = "EL0T",
.psr = ARMV8_64_EL0T,
armv8_state_strings[arm->core_state]);
}
+static void armv8_show_fault_registers32(struct armv8_common *armv8)
+{
+ uint32_t dfsr, ifsr, dfar, ifar;
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ int retval;
+
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ return;
+
+ /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+
+ /* c5/c0 - {data, instruction} fault status registers */
+ retval = dpm->instr_read_data_r0(dpm,
+ T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 0)),
+ &dfsr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 1)),
+ &ifsr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* c6/c0 - {data, instruction} fault address registers */
+ retval = dpm->instr_read_data_r0(dpm,
+ T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 0)),
+ &dfar);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 2)),
+ &ifar);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ ", DFAR: %8.8" PRIx32, dfsr, dfar);
+ LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ ", IFAR: %8.8" PRIx32, ifsr, ifar);
+
+done:
+ /* (void) */ dpm->finish(dpm);
+}
+
static void armv8_show_fault_registers(struct target *target)
{
- /* TODO */
+ struct armv8_common *armv8 = target_to_armv8(target);
+
+ if (armv8->arm.core_state != ARM_STATE_AARCH64)
+ armv8_show_fault_registers32(armv8);
}
static uint8_t armv8_pa_size(uint32_t ps)
return ret;
}
+static int armv8_read_ttbcr32(struct target *target)
+{
+ struct armv8_common *armv8 = target_to_armv8(target);
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ uint32_t ttbcr, ttbcr_n;
+ int retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+ /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
+ retval = dpm->instr_read_data_r0(dpm,
+ T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 2, 0, 2)),
+ &ttbcr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+
+ ttbcr_n = ttbcr & 0x7;
+ armv8->armv8_mmu.ttbcr = ttbcr;
+
+ /*
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * document # ARM DDI 0406C
+ */
+ armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
+ armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
+ armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+ armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
+
+ LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+ (ttbcr_n != 0) ? "used" : "not used",
+ armv8->armv8_mmu.ttbr_mask[0],
+ armv8->armv8_mmu.ttbr_mask[1]);
+
+done:
+ dpm->finish(dpm);
+ return retval;
+}
+
static int armv8_read_ttbcr(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
return retval;
}
-static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
+static int armv8_4K_translate(struct target *target, target_addr_t va, target_addr_t *val)
{
LOG_ERROR("4K page Address translation need to add");
return ERROR_FAIL;
/* method adapted to cortex A : reused arm v4 v5 method*/
-int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
+int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
{
int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
uint32_t mpidr;
+
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
/* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_MPIDR, 0),
- &mpidr);
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
if (retval != ERROR_OK)
goto done;
if (mpidr & 1<<31) {
uint32_t cache_selected, clidr;
uint32_t cache_i_reg, cache_d_reg;
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
- armv8_read_ttbcr(target);
- retval = dpm->prepare(dpm);
+ int is_aarch64 = armv8->arm.core_state == ARM_STATE_AARCH64;
+
+ retval = is_aarch64 ? armv8_read_ttbcr(target) : armv8_read_ttbcr32(target);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
- /* retrieve CLIDR
- * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CLIDR, 0),
- &clidr);
+
+ /* retrieve CLIDR */
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
if (retval != ERROR_OK)
goto done;
+
clidr = (clidr & 0x7000000) >> 23;
LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
if ((clidr / 2) > 1) {
LOG_ERROR("cache l2 present :not supported");
}
/* retrieve selected cache*/
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- &cache_selected);
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CSSELR), &cache_selected);
if (retval != ERROR_OK)
goto done;
-
/* select instruction cache
* [0] : 1 instruction cache selection , 0 data cache selection */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- 1);
+ retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 1);
if (retval != ERROR_OK)
goto done;
* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
* [2:0] line size 001 eight word per line
* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
- &cache_i_reg);
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_i_reg);
if (retval != ERROR_OK)
goto done;
/* select data cache*/
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- 0);
+ retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 0);
if (retval != ERROR_OK)
goto done;
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
- &cache_d_reg);
+ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_d_reg);
if (retval != ERROR_OK)
goto done;
/* restore selected cache */
- dpm->instr_write_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CSSELR, 0),
- cache_selected);
-
+ dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), cache_selected);
if (retval != ERROR_OK)
goto done;
dpm->finish(dpm);
if (arm->core_mode == ARM_MODE_ABT)
armv8_show_fault_registers(target);
+
if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x",
(unsigned) armv8->dpm.wp_pc);
const char *group;
const char *feature;
} armv8_regs[] = {
- { ARMV8_R0, "x0", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R1, "x1", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R2, "x2", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R3, "x3", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R4, "x4", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R5, "x5", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R6, "x6", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R7, "x7", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R8, "x8", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R9, "x9", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R10, "x10", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R11, "x11", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R12, "x12", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R13, "x13", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R14, "x14", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R15, "x15", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R16, "x16", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R17, "x17", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R18, "x18", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R19, "x19", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R20, "x20", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R21, "x21", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R22, "x22", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R23, "x23", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R24, "x24", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R25, "x25", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R26, "x26", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R27, "x27", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R28, "x28", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R29, "x29", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_R30, "x30", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R0, "x0", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R1, "x1", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R2, "x2", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R3, "x3", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R4, "x4", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R5, "x5", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R6, "x6", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R7, "x7", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R8, "x8", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R9, "x9", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R10, "x10", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R11, "x11", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R12, "x12", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R13, "x13", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R14, "x14", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R15, "x15", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R16, "x16", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R17, "x17", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R18, "x18", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R19, "x19", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R20, "x20", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R21, "x21", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R22, "x22", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R23, "x23", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R24, "x24", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R25, "x25", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R26, "x26", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R27, "x27", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R28, "x28", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R29, "x29", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_R30, "x30", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
{ ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
{ ARMV8_PC, "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
- { ARMV8_xPSR, "CPSR", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
+ { ARMV8_xPSR, "CPSR", 32, REG_TYPE_UINT32, "general", "org.gnu.gdb.aarch64.core" },
};
#define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
{
struct arm_reg *armv8_reg = reg->arch_info;
struct target *target = armv8_reg->target;
+ struct arm *arm = target_to_arm(target);
uint64_t value = buf_get_u64(buf, 0, 64);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- buf_set_u64(reg->value, 0, 64, value);
+ if (reg == arm->cpsr) {
+ armv8_set_cpsr(arm, (uint32_t)value);
+ } else {
+ buf_set_u64(reg->value, 0, 64, value);
+ reg->valid = 1;
+ }
+
reg->dirty = 1;
- reg->valid = 1;
return ERROR_OK;
}
reg_list[i].name = armv8_regs[i].name;
reg_list[i].size = armv8_regs[i].bits;
- reg_list[i].value = calloc(1, 4);
+ reg_list[i].value = calloc(1, 8);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].type = &armv8_reg_type;