coding style: fix space separation

[openocd.git] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 0c85086619b1f52d7b912627c23e9edb8e757fd8..4f1ebce88fcf6dd856ce82bc9b6abf802da49742 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1288,13 +1288,13 @@ static struct reg_data_type aarch64v[] = {
 };
 
 static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
-       {  0, 0 , REG_TYPE_UINT8 },
-       {  2, 3,  REG_TYPE_UINT8 },
-       {  4, 4 , REG_TYPE_UINT8 },
-       {  6, 6 , REG_TYPE_BOOL },
-       {  7, 7 , REG_TYPE_BOOL },
-       {  8, 8 , REG_TYPE_BOOL },
-       {  9, 9 , REG_TYPE_BOOL },
+       {  0,  0, REG_TYPE_UINT8 },
+       {  2,  3, REG_TYPE_UINT8 },
+       {  4,  4, REG_TYPE_UINT8 },
+       {  6,  6, REG_TYPE_BOOL },
+       {  7,  7, REG_TYPE_BOOL },
+       {  8,  8, REG_TYPE_BOOL },
+       {  9,  9, REG_TYPE_BOOL },
        { 20, 20, REG_TYPE_BOOL },
        { 21, 21, REG_TYPE_BOOL },
        { 28, 28, REG_TYPE_BOOL },
@@ -1307,16 +1307,16 @@ static struct reg_data_type_flags_field aarch64_cpsr_fields[] = {
        { "SP",  aarch64_cpsr_bits + 0,  aarch64_cpsr_fields + 1 },
        { "EL",  aarch64_cpsr_bits + 1,  aarch64_cpsr_fields + 2 },
        { "nRW", aarch64_cpsr_bits + 2,  aarch64_cpsr_fields + 3 },
-       { "F"  , aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
-       { "I"  , aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
-       { "A"  , aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
-       { "D"  , aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
-       { "IL" , aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
-       { "SS" , aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
-       { "V"  , aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
-       { "C"  , aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
-       { "Z"  , aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
-       { "N"  , aarch64_cpsr_bits + 12, NULL }
+       { "F",   aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
+       { "I",   aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
+       { "A",   aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
+       { "D",   aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
+       { "IL",  aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
+       { "SS",  aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
+       { "V",   aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
+       { "C",   aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
+       { "Z",   aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
+       { "N",   aarch64_cpsr_bits + 12, NULL }
 };
 
 static struct reg_data_type_flags aarch64_cpsr_flags[] = {