ARMv7-M: make DAP commands verify target is an ARMv7-M

[openocd.git] / src / target / armv7m.h

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index dba9a3bdf1bc9c51274b08ecb24518d55453c2e4..b6be1d22497e340ed542463a0df4e0b9efca4708 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -27,12 +27,19 @@
 #define ARMV7M_COMMON_H
 
 #include "arm_adi_v5.h"
+#include "arm.h"
 
 /* define for enabling armv7 gdb workarounds */
 #if 1
 #define ARMV7_GDB_HACKS
 #endif
 
+#ifdef ARMV7_GDB_HACKS
+extern uint8_t armv7m_gdb_dummy_cpsr_value[];
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
+#endif
+
+
 enum armv7m_mode
 {
        ARMV7M_MODE_THREAD = 0,
@@ -99,9 +106,14 @@ struct armv7m_common
        int exception_number;
        struct swjdp_common swjdp_info;
 
+       uint32_t demcr;
+
        /* Direct processor core register read and writes */
-       int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
-       int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
+       int (*load_core_reg_u32)(struct target *target,
+               enum armv7m_regtype type, uint32_t num, uint32_t *value);
+       int (*store_core_reg_u32)(struct target *target,
+               enum armv7m_regtype type, uint32_t num, uint32_t value);
+
        /* register cache to processor synchronization */
        int (*read_core_reg)(struct target *target, unsigned num);
        int (*write_core_reg)(struct target *target, unsigned num);
@@ -119,6 +131,11 @@ target_to_armv7m(struct target *target)
        return target->arch_info;
 }
 
+static inline bool is_armv7m(struct armv7m_common *armv7m)
+{
+       return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
+}
+
 struct armv7m_algorithm
 {
        int common_magic;
@@ -142,7 +159,6 @@ int armv7m_arch_state(struct target *target);
 int armv7m_get_gdb_reg_list(struct target *target,
                struct reg **reg_list[], int *reg_list_size);
 
-int armv7m_register_commands(struct command_context *cmd_ctx);
 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 
 int armv7m_run_algorithm(struct target *target,
@@ -160,83 +176,8 @@ int armv7m_checksum_memory(struct target *target,
 int armv7m_blank_check_memory(struct target *target,
                uint32_t address, uint32_t count, uint32_t* blank);
 
-/* Thumb mode instructions
- */
-
-/* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
- * Rd: destination register
- * SYSm: source special register
- */
-#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
-
-/* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
- * Rd: source register
- * SYSm: destination special register
- */
-#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
-
-/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
- * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
- * Rd: source register
- * IF:
- */
-#define I_FLAG 2
-#define F_FLAG 1
-#define ARMV7M_T_CPSID(IF)     ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
-#define ARMV7M_T_CPSIE(IF)     ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
-
-/* Breakpoint (Thumb mode) v5 onwards
- * Im: immediate value used by debugger
- */
-#define ARMV7M_T_BKPT(Im)      ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
-
-/* Store register (Thumb mode)
- * Rd: source register
- * Rn: base register
- */
-#define ARMV7M_T_STR(Rd, Rn)   ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
-
-/* Load register (Thumb state)
- * Rd: destination register
- * Rn: base register
- */
-#define ARMV7M_T_LDR(Rd, Rn)   ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
-
-/* Load multiple (Thumb state)
- * Rn: base register
- * List: for each bit in list: store register
- */
-#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
-
-/* Load register with PC relative addressing
- * Rd: register to load
- */
-#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
-
-/* Move hi register (Thumb mode)
- * Rd: destination register
- * Rm: source register
- */
-#define ARMV7M_T_MOV(Rd, Rm)   ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
-
-/* No operation (Thumb mode)
- */
-#define ARMV7M_T_NOP   (0x46c0 | (0x46c0 << 16))
-
-/* Move immediate to register (Thumb state)
- * Rd: destination register
- * Im: 8-bit immediate value
- */
-#define ARMV7M_T_MOV_IM(Rd, Im)        ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
-
-/* Branch and Exchange
- * Rm: register containing branch target
- */
-#define ARMV7M_T_BX(Rm)                ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
-
-/* Branch (Thumb state)
- * Imm: Branch target
- */
-#define ARMV7M_T_B(Imm)        ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
+int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
+
+extern const struct command_registration armv7m_command_handlers[];
 
 #endif /* ARMV7M_H */