Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
Cleanup: nuke trailling whitespaces
[openocd.git] / src / target / armv7m.c
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 5849443018afb4c75481110bc3dae203db8e85c8..75a2fb9e3b3b12607fbf2153d9c291ecc84b865e 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -26,7 +26,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  *                                                                         *
- *     ARMv7-M Architecture, Application Level Reference Manual           *
+ *     ARMv7-M Architecture, Application Level Reference Manual               *
  *              ARM DDI 0405C (September 2008)                             *
  *                                                                         *
  ***************************************************************************/
@@ -36,6 +36,8 @@
 
 #include "armv7m.h"
 
+#define ARRAY_SIZE(x)  ((int)(sizeof(x)/sizeof((x)[0])))
+
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
@@ -46,7 +48,7 @@ char* armv7m_mode_strings[] =
        "Thread", "Thread (User)", "Handler",
 };
 
-char* armv7m_exception_strings[] =
+static char *armv7m_exception_strings[] =
 {
        "", "Reset", "NMI", "HardFault",
        "MemManage", "BusFault", "UsageFault", "RESERVED",
@@ -54,16 +56,6 @@ char* armv7m_exception_strings[] =
        "DebugMonitor", "RESERVED", "PendSV", "SysTick"
 };
 
-char* armv7m_core_reg_list[] =
-{
-       /* Registers accessed through core debug */
-       "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
-       "sp", "lr", "pc",
-       "xPSR", "msp", "psp",
-       /* Registers accessed through special reg 20 */
-       "primask", "basepri", "faultmask", "control"
-};
-
 uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t armv7m_gdb_dummy_fp_reg =
@@ -87,37 +79,48 @@ reg_t armv7m_gdb_dummy_cpsr_reg =
 };
 #endif
 
-armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
-{
-       /*  CORE_GP are accesible using the core debug registers */
-       {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-       {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-
-       {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
-       {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
-       {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
-
-       /*  CORE_SP are accesible using coreregister 20 */
-       {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
-       {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
-       {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
-       {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}  /* CONTROL */
+/*
+ * These registers are not memory-mapped.  The ARMv7-M profile includes
+ * memory mapped registers too, such as for the NVIC (interrupt controller)
+ * and SysTick (timer) modules; those can mostly be treated as peripherals.
+ */
+static const struct {
+       unsigned id;
+       char *name;
+       unsigned bits;
+} armv7m_regs[] = {
+       { ARMV7M_R0, "r0", 32 },
+       { ARMV7M_R1, "r1", 32 },
+       { ARMV7M_R2, "r2", 32 },
+       { ARMV7M_R3, "r3", 32 },
+
+       { ARMV7M_R4, "r4", 32 },
+       { ARMV7M_R5, "r5", 32 },
+       { ARMV7M_R6, "r6", 32 },
+       { ARMV7M_R7, "r7", 32 },
+
+       { ARMV7M_R8, "r8", 32 },
+       { ARMV7M_R9, "r9", 32 },
+       { ARMV7M_R10, "r10", 32 },
+       { ARMV7M_R11, "r11", 32 },
+
+       { ARMV7M_R12, "r12", 32 },
+       { ARMV7M_R13, "sp", 32 },
+       { ARMV7M_R14, "lr", 32 },
+       { ARMV7M_PC, "pc", 32 },
+
+       { ARMV7M_xPSR, "xPSR", 32 },
+       { ARMV7M_MSP, "msp", 32 },
+       { ARMV7M_PSP, "psp", 32 },
+
+       { ARMV7M_PRIMASK, "primask", 1 },
+       { ARMV7M_BASEPRI, "basepri", 8 },
+       { ARMV7M_FAULTMASK, "faultmask", 1 },
+       { ARMV7M_CONTROL, "control", 2 },
 };
 
+#define ARMV7M_NUM_REGS        ARRAY_SIZE(armv7m_regs)
+
 int armv7m_core_reg_arch_type = -1;
 int armv7m_dummy_core_reg_arch_type = -1;
 
@@ -133,7 +136,7 @@ int armv7m_restore_context(target_t *target)
        if (armv7m->pre_restore_context)
                armv7m->pre_restore_context(target);
 
-       for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
+       for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
        {
                if (armv7m->core_cache->reg_list[i].dirty)
                {
@@ -204,7 +207,7 @@ int armv7m_read_core_reg(struct target_s *target, int num)
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
 
-       if ((num < 0) || (num >= ARMV7NUMCOREREGS))
+       if ((num < 0) || (num >= ARMV7M_NUM_REGS))
                return ERROR_INVALID_ARGUMENTS;
 
        armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
@@ -225,7 +228,7 @@ int armv7m_write_core_reg(struct target_s *target, int num)
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
 
-       if ((num < 0) || (num >= ARMV7NUMCOREREGS))
+       if ((num < 0) || (num >= ARMV7M_NUM_REGS))
                return ERROR_INVALID_ARGUMENTS;
 
        reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
@@ -268,6 +271,13 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
        *reg_list_size = 26;
        *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 
+       /*
+        * GDB register packet format for ARM:
+        *  - the first 16 registers are r0..r15
+        *  - (obsolete) 8 FPA registers
+        *  - (obsolete) FPA status
+        *  - CPSR
+        */
        for (i = 0; i < 16; i++)
        {
                (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
@@ -337,7 +347,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
        enum armv7m_mode core_mode = armv7m->core_mode;
        int retval = ERROR_OK;
        int i;
-       uint32_t context[ARMV7NUMCOREREGS];
+       uint32_t context[ARMV7M_NUM_REGS];
 
        if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
        {
@@ -353,7 +363,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
 
        /* refresh core register cache */
        /* Not needed if core register cache is always consistent with target process state */
-       for (i = 0; i < ARMV7NUMCOREREGS; i++)
+       for (i = 0; i < ARMV7M_NUM_REGS; i++)
        {
                if (!armv7m->core_cache->reg_list[i].valid)
                        armv7m->read_core_reg(target, i);
@@ -390,7 +400,8 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
        if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
        {
                LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
-               buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
+               buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
+                               0, 1, armv7m_algorithm_info->core_mode);
                armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
                armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
        }
@@ -444,14 +455,16 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
                }
        }
 
-       for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
+       for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
        {
                uint32_t regvalue;
                regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
                if (regvalue != context[i])
                {
-                       LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
-                       buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
+                       LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+                               armv7m->core_cache->reg_list[i].name, context[i]);
+                       buf_set_u32(armv7m->core_cache->reg_list[i].value,
+                                       0, 32, context[i]);
                        armv7m->core_cache->reg_list[i].valid = 1;
                        armv7m->core_cache->reg_list[i].dirty = 1;
                }
@@ -466,13 +479,21 @@ int armv7m_arch_state(struct target_s *target)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
+       uint32_t ctrl, sp;
+
+       ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
+       sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
-       LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
-                Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
+       LOG_USER("target halted due to %s, current mode: %s %s\n"
+               "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
+               Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+                               target->debug_reason)->name,
                armv7m_mode_strings[armv7m->core_mode],
                armv7m_exception_string(armv7m->exception_number),
                buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
-               buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
+               buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
+               (ctrl & 0x02) ? 'p' : 'm',
+               sp);
 
        return ERROR_OK;
 }
@@ -482,11 +503,11 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target)
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
 
-       int num_regs = ARMV7NUMCOREREGS;
+       int num_regs = ARMV7M_NUM_REGS;
        reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
        reg_cache_t *cache = malloc(sizeof(reg_cache_t));
-       reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
-       armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
+       reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
+       armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t));
        int i;
 
        if (armv7m_core_reg_arch_type == -1)
@@ -510,11 +531,11 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target)
 
        for (i = 0; i < num_regs; i++)
        {
-               arch_info[i] = armv7m_core_reg_list_arch_info[i];
+               arch_info[i].num = armv7m_regs[i].id;
                arch_info[i].target = target;
                arch_info[i].armv7m_common = armv7m;
-               reg_list[i].name = armv7m_core_reg_list[i];
-               reg_list[i].size = 32;
+               reg_list[i].name = armv7m_regs[i].name;
+               reg_list[i].size = armv7m_regs[i].bits;
                reg_list[i].value = calloc(1, 4);
                reg_list[i].dirty = 0;
                reg_list[i].valid = 0;
@@ -552,7 +573,7 @@ int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
        reg_param_t reg_params[2];
        int retval;
 
-       uint16_t cortex_m3_crc_code[] = {
+       static const uint16_t cortex_m3_crc_code[] = {
                0x4602,                                 /* mov  r2, r0 */
                0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
                0x460B,                                 /* mov  r3, r1 */
@@ -634,11 +655,11 @@ int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_
        int retval;
        uint32_t i;
 
-       uint16_t erase_check_code[] =
+       static const uint16_t erase_check_code[] =
        {
                                                        /* loop: */
-               0xF810, 0x3B01,         /* ldrb         r3, [r0], #1 */
-               0xEA02, 0x0203,         /* and  r2, r2, r3 */
+               0xF810, 0x3B01,         /* ldrb r3, [r0], #1 */
+               0xEA02, 0x0203,         /* and  r2, r2, r3 */
                0x3901,                         /* subs         r1, r1, #1 */
                0xD1F9,                         /* bne          loop */
                                                        /* end: */
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)