* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
+
#ifndef ARMV4_5_H
#define ARMV4_5_H
-#include <target/target.h>
-#include <helper/command.h>
-
-
-/**
- * These numbers match the five low bits of the *PSR registers on
- * "classic ARM" processors, which build on the ARMv4 processor
- * modes and register set.
+/* This stuff "knows" that its callers aren't talking
+ * to microcontroller profile (current Cortex-M) parts.
+ * We want to phase it out so core code can be shared.
*/
-enum arm_mode {
- ARM_MODE_USR = 16,
- ARM_MODE_FIQ = 17,
- ARM_MODE_IRQ = 18,
- ARM_MODE_SVC = 19,
- ARM_MODE_ABT = 23,
- ARM_MODE_MON = 26,
- ARM_MODE_UND = 27,
- ARM_MODE_SYS = 31,
- ARM_MODE_ANY = -1
-};
-
-const char *arm_mode_name(unsigned psr_mode);
-bool is_arm_mode(unsigned psr_mode);
-
-/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
-enum arm_state {
- ARM_STATE_ARM,
- ARM_STATE_THUMB,
- ARM_STATE_JAZELLE,
- ARM_STATE_THUMB_EE,
-};
-
-extern const char *arm_state_strings[];
/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
* index into the armv4_5_core_reg_map array. Its remaining users are
extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
- cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
+ (cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
enum { ARMV4_5_CPSR = 31, };
-#define ARM_COMMON_MAGIC 0x0A450A45
-
-/**
- * Represents a generic ARM core, with standard application registers.
- *
- * There are sixteen application registers (including PC, SP, LR) and a PSR.
- * Cortex-M series cores do not support as many core states or shadowed
- * registers as traditional ARM cores, and only support Thumb2 instructions.
- */
-struct arm
-{
- int common_magic;
- struct reg_cache *core_cache;
-
- /** Handle to the CPSR; valid in all core modes. */
- struct reg *cpsr;
-
- /** Handle to the SPSR; valid only in core modes with an SPSR. */
- struct reg *spsr;
-
- /** Support for arm_reg_current() */
- const int *map;
-
- /**
- * Indicates what registers are in the ARM state core register set.
- * ARM_MODE_ANY indicates the standard set of 37 registers,
- * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
- * more registers are shadowed, for "Secure Monitor" mode.
- */
- enum arm_mode core_type;
-
- /** Record the current core mode: SVC, USR, or some other mode. */
- enum arm_mode core_mode;
-
- /** Record the current core state: ARM, Thumb, or otherwise. */
- enum arm_state core_state;
-
- /** Flag reporting unavailability of the BKPT instruction. */
- bool is_armv4;
-
- /** Flag reporting whether semihosting is active. */
- bool is_semihosting;
-
- /** Value to be returned by semihosting SYS_ERRNO request. */
- int semihosting_errno;
-
- /** Backpointer to the target. */
- struct target *target;
-
- /** Handle for the debug module, if one is present. */
- struct arm_dpm *dpm;
-
- /** Handle for the Embedded Trace Module, if one is present. */
- struct etm_context *etm;
-
- /* FIXME all these methods should take "struct arm *" not target */
-
- /** Retrieve all core registers, for display. */
- int (*full_context)(struct target *target);
-
- /** Retrieve a single core register. */
- int (*read_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode);
- int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode, uint32_t value);
-
- /** Read coprocessor register. */
- int (*mrc)(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t *value);
-
- /** Write coprocessor register. */
- int (*mcr)(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t value);
-
- void *arch_info;
-};
-
-/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target *target)
-{
- return target->arch_info;
-}
-
-static inline bool is_arm(struct arm *arm)
-{
- return arm && arm->common_magic == ARM_COMMON_MAGIC;
-}
-
-struct arm_algorithm
-{
- int common_magic;
-
- enum arm_mode core_mode;
- enum arm_state core_state;
-};
-
-struct arm_reg
-{
- int num;
- enum arm_mode mode;
- struct target *target;
- struct arm *armv4_5_common;
- uint32_t value;
-};
-
-struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
-
-int armv4_5_arch_state(struct target *target);
-int armv4_5_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
-
-extern const struct command_registration arm_command_handlers[];
-
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
-
-int armv4_5_run_algorithm(struct target *target,
- int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info);
-
-int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum);
-int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
-
-void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-
-extern struct reg arm_gdb_dummy_fp_reg;
-extern struct reg arm_gdb_dummy_fps_reg;
-
#endif /* ARMV4_5_H */
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