switch (regnum) {
case 0 ... 30:
i = 0xd5330400 + regnum;
- retval = dpm->instr_write_data_dcc(dpm, i, value);
+ retval = dpm->instr_write_data_dcc_64(dpm, i, value);
+ break;
+ case 32: /* PC */
+ i = 0xd51b4520;
+ retval = dpm->instr_write_data_r0_64(dpm, i, value);
break;
-
default:
+ LOG_DEBUG("register %s (%16.16llx) not defined", r->name,
+ (unsigned long long)value);
break;
}
/* update core mode and state, plus shadow mapping for R8..R14 */
arm_set_cpsr(arm, cpsr);
+ if (core_state == ARM_STATE_AARCH64)
+ /* arm_set_cpsr changes core_state, restore it for now */
+ arm->core_state = ARM_STATE_AARCH64;
core_regs = arm->core_cache->num_regs;
*/
/* check everything except our scratch register R0 */
- for (unsigned i = 1; i < 32; i++) {
+ for (unsigned i = 1; i <= 32; i++) {
struct arm_reg *r;
unsigned regnum;
{
struct arm *arm = dpm->arm;
struct target *target = arm->target;
- struct reg_cache *cache;
+ struct reg_cache *cache = 0;
arm->dpm = dpm;
arm->read_core_reg = arm->read_core_reg ? : arm_dpm_read_core_reg;
arm->write_core_reg = arm->write_core_reg ? : arm_dpm_write_core_reg;
- /* avoid duplicating the register cache */
- if (arm->core_cache == NULL) {
- cache = arm_build_reg_cache(target, arm);
+ if (arm->core_cache != NULL) {
+ if (arm->core_state == ARM_STATE_AARCH64) {
+ cache = armv8_build_reg_cache(target);
+ target->reg_cache = cache;
+ } else {
+ cache = arm_build_reg_cache(target, arm);
+ *register_get_last_cache_p(&target->reg_cache) = cache;
+ }
+
if (!cache)
return ERROR_FAIL;
-
- *register_get_last_cache_p(&target->reg_cache) = cache;
}
/* coprocessor access setup */