Fix warnings exposed by GCC8

[openocd.git] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 1536679367984fa65c8ae012888f47f89c41d070..17948d6da49beecd893c997e544f8d9a0e9eebdd 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -170,6 +170,18 @@ static int evaluate_pld(uint32_t opcode,
 
                return ERROR_OK;
        }
+       /* ISB */
+       if ((opcode & 0x07f000f0) == 0x05700060) {
+               instruction->type = ARM_ISB;
+
+               snprintf(instruction->text,
+                               128,
+                               "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB %s",
+                               address, opcode,
+                               ((opcode & 0x0000000f) == 0xf) ? "SY" : "UNK");
+
+               return ERROR_OK;
+       }
        return evaluate_unknown(opcode, address, instruction);
 }
 
@@ -1537,7 +1549,7 @@ static int evaluate_misc_instr(uint32_t opcode,
                }
 
                /* SMLAW < y> */
-               if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) {
+               if (((opcode & 0x00600000) == 0x00200000) && (x == 0)) {
                        uint8_t Rd, Rm, Rs, Rn;
                        instruction->type = ARM_SMLAWy;
                        Rd = (opcode & 0xf0000) >> 16;
@@ -1559,7 +1571,7 @@ static int evaluate_misc_instr(uint32_t opcode,
                }
 
                /* SMUL < x><y> */
-               if ((opcode & 0x00600000) == 0x00300000) {
+               if ((opcode & 0x00600000) == 0x00600000) {
                        uint8_t Rd, Rm, Rs;
                        instruction->type = ARM_SMULxy;
                        Rd = (opcode & 0xf0000) >> 16;
@@ -1580,7 +1592,7 @@ static int evaluate_misc_instr(uint32_t opcode,
                }
 
                /* SMULW < y> */
-               if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) {
+               if (((opcode & 0x00600000) == 0x00200000) && (x == 1)) {
                        uint8_t Rd, Rm, Rs;
                        instruction->type = ARM_SMULWy;
                        Rd = (opcode & 0xf0000) >> 16;
@@ -1603,6 +1615,33 @@ static int evaluate_misc_instr(uint32_t opcode,
        return ERROR_OK;
 }
 
+static int evaluate_mov_imm(uint32_t opcode,
+                             uint32_t address, struct arm_instruction *instruction)
+{
+       uint16_t immediate;
+       uint8_t Rd;
+       bool T;
+
+       Rd = (opcode & 0xf000) >> 12;
+       T = opcode & 0x00400000;
+       immediate = (opcode & 0xf0000) >> 4 | (opcode & 0xfff);
+
+       instruction->type = ARM_MOV;
+       instruction->info.data_proc.Rd = Rd;
+
+       snprintf(instruction->text,
+                128,
+                "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMOV%s%s r%i, #0x%" PRIx16,
+                address,
+                opcode,
+                T ? "T" : "W",
+                COND(opcode),
+                Rd,
+                immediate);
+
+       return ERROR_OK;
+}
+
 static int evaluate_data_proc(uint32_t opcode,
                              uint32_t address, struct arm_instruction *instruction)
 {
@@ -1879,16 +1918,9 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 
        /* catch opcodes with [27:25] = b001 */
        if ((opcode & 0x0e000000) == 0x02000000) {
-               /* Undefined instruction */
-               if ((opcode & 0x0fb00000) == 0x03000000) {
-                       instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text,
-                                       128,
-                                       "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
-                                       address,
-                                       opcode);
-                       return ERROR_OK;
-               }
+               /* 16-bit immediate load */
+               if ((opcode & 0x0fb00000) == 0x03000000)
+                       return evaluate_mov_imm(opcode, address, instruction);
 
                /* Move immediate to status register */
                if ((opcode & 0x0fb00000) == 0x03200000)
@@ -2946,6 +2978,7 @@ static int t2ev_b_bl(uint32_t opcode, uint32_t address,
        case 0x4:
                inst = "BLX";
                instruction->type = ARM_BLX;
+               address &= 0xfffffffc;
                break;
        case 0x5:
                inst = "BL";