/*
* Relevant specifications from ARM include:
*
- * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
+ * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
* CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
*
* CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
#include "jtag/interface.h"
#include "arm.h"
#include "arm_adi_v5.h"
+#include "jtag/swd.h"
+#include "transport/transport.h"
#include <helper/jep106.h>
#include <helper/time_support.h>
#include <helper/list.h>
dap_invalidate_cache(dap);
+ /*
+ * Early initialize dap->dp_ctrl_stat.
+ * In jtag mode only, if the following atomic reads fail and set the
+ * sticky error, it will trigger the clearing of the sticky. Without this
+ * initialization system and debug power would be disabled while clearing
+ * the sticky error bit.
+ */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+
for (size_t i = 0; i < 30; i++) {
/* DP initialization */
break;
}
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ /*
+ * This write operation clears the sticky error bit in jtag mode only and
+ * is ignored in swd mode. It also powers-up system and debug domains in
+ * both jtag and swd modes, if not done before.
+ * Actually we do not need to clear the sticky error here because it has
+ * been already cleared (if it was set) in the previous atomic read. This
+ * write could be removed, but this initial part of dap_dp_init() is the
+ * result of years of fine tuning and there are strong concerns about any
+ * unnecessary code change. It doesn't harm, so let's keep it here and
+ * preserve the historical sequence of read/write operations!
+ */
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
+/**
+ * Put the debug link into SWD mode, if the target supports it.
+ * The link's initial mode may be either JTAG (for example,
+ * with SWJ-DP after reset) or SWD.
+ *
+ * Note that targets using the JTAG-DP do not support SWD, and that
+ * some targets which could otherwise support it may have been
+ * configured to disable SWD signaling
+ *
+ * @param dap The DAP used
+ * @return ERROR_OK or else a fault code.
+ */
+int dap_to_swd(struct adiv5_dap *dap)
+{
+ int retval;
+
+ LOG_DEBUG("Enter SWD mode");
+
+ if (transport_is_jtag()) {
+ retval = jtag_add_tms_seq(swd_seq_jtag_to_swd_len,
+ swd_seq_jtag_to_swd, TAP_INVALID);
+ if (retval == ERROR_OK)
+ retval = jtag_execute_queue();
+ return retval;
+ }
+
+ if (transport_is_swd()) {
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+
+ return swd->switch_seq(JTAG_TO_SWD);
+ }
+
+ LOG_ERROR("Nor JTAG nor SWD transport");
+ return ERROR_FAIL;
+}
+
+/**
+ * Put the debug link into JTAG mode, if the target supports it.
+ * The link's initial mode may be either SWD or JTAG.
+ *
+ * Note that targets implemented with SW-DP do not support JTAG, and
+ * that some targets which could otherwise support it may have been
+ * configured to disable JTAG signaling
+ *
+ * @param dap The DAP used
+ * @return ERROR_OK or else a fault code.
+ */
+int dap_to_jtag(struct adiv5_dap *dap)
+{
+ int retval;
+
+ LOG_DEBUG("Enter JTAG mode");
+
+ if (transport_is_jtag()) {
+ retval = jtag_add_tms_seq(swd_seq_swd_to_jtag_len,
+ swd_seq_swd_to_jtag, TAP_RESET);
+ if (retval == ERROR_OK)
+ retval = jtag_execute_queue();
+ return retval;
+ }
+
+ if (transport_is_swd()) {
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+
+ return swd->switch_seq(SWD_TO_JTAG);
+ }
+
+ LOG_ERROR("Nor JTAG nor SWD transport");
+ return ERROR_FAIL;
+}
+
/* CID interpretation -- see ARM IHI 0029B section 3
* and ARM IHI 0031A table 13-3.
*/
{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
-static int dap_rom_display(struct command_context *cmd_ctx,
+static int dap_rom_display(struct command_invocation *cmd,
struct adiv5_ap *ap, uint32_t dbgbase, int depth)
{
int retval;
char tabs[16] = "";
if (depth > 16) {
- command_print(cmd_ctx, "\tTables too deep");
+ command_print(cmd->ctx, "\tTables too deep");
return ERROR_FAIL;
}
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
uint32_t base_addr = dbgbase & 0xFFFFF000;
- command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
+ command_print(cmd->ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
- command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
+ command_print(cmd->ctx, "\t\tCan't read component, the corresponding core might be turned off");
return ERROR_OK; /* Don't abort recursion */
}
if (!is_dap_cid_ok(cid)) {
- command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
+ command_print(cmd->ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
return ERROR_OK; /* Don't abort recursion */
}
/* component may take multiple 4K pages */
uint32_t size = (pid >> 36) & 0xf;
if (size > 0)
- command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
+ command_print(cmd->ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
- command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
+ command_print(cmd->ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
uint8_t class = (cid >> 12) & 0xf;
uint16_t part_num = pid & 0xfff;
if (designer_id & 0x80) {
/* JEP106 code */
- command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+ command_print(cmd->ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
- command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+ command_print(cmd->ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
}
break;
}
- command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
- command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
+ command_print(cmd->ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
+ command_print(cmd->ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
if (class == 1) { /* ROM Table */
uint32_t memtype;
return retval;
if (memtype & 0x01)
- command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
+ command_print(cmd->ctx, "\t\tMEMTYPE system memory present on bus");
else
- command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
+ command_print(cmd->ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
+ command_print(cmd->ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
tabs, entry_offset, romentry);
if (romentry & 0x01) {
/* Recurse */
- retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
+ retval = dap_rom_display(cmd, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
if (retval != ERROR_OK)
return retval;
} else if (romentry != 0) {
- command_print(cmd_ctx, "\t\tComponent not present");
+ command_print(cmd->ctx, "\t\tComponent not present");
} else {
- command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
+ command_print(cmd->ctx, "\t%s\tEnd of ROM table", tabs);
break;
}
}
}
break;
case 6:
- major = "Perfomance Monitor";
+ major = "Performance Monitor";
switch (minor) {
case 0:
subtype = "other";
}
break;
}
- command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+ command_print(cmd->ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
(uint8_t)(devtype & 0xff),
major, subtype);
/* REVISIT also show 0xfc8 DevId */
return ERROR_OK;
}
-int dap_info_command(struct command_context *cmd_ctx,
+int dap_info_command(struct command_invocation *cmd,
struct adiv5_ap *ap)
{
int retval;
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
+ command_print(cmd->ctx, "AP ID register 0x%8.8" PRIx32, apid);
if (apid == 0) {
- command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
+ command_print(cmd->ctx, "No AP found at this ap 0x%x", ap->ap_num);
return ERROR_FAIL;
}
switch (apid & (IDR_JEP106 | IDR_TYPE)) {
case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
- command_print(cmd_ctx, "\tType is JTAG-AP");
+ command_print(cmd->ctx, "\tType is JTAG-AP");
break;
case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AHB");
+ command_print(cmd->ctx, "\tType is MEM-AP AHB");
break;
case IDR_JEP106_ARM | AP_TYPE_APB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP APB");
+ command_print(cmd->ctx, "\tType is MEM-AP APB");
break;
case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AXI");
+ command_print(cmd->ctx, "\tType is MEM-AP AXI");
break;
default:
- command_print(cmd_ctx, "\tUnknown AP type");
+ command_print(cmd->ctx, "\tUnknown AP type");
break;
}
*/
mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
if (mem_ap) {
- command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
+ command_print(cmd->ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
- command_print(cmd_ctx, "\tNo ROM table present");
+ command_print(cmd->ctx, "\tNo ROM table present");
} else {
if (dbgbase & 0x01)
- command_print(cmd_ctx, "\tValid ROM table present");
+ command_print(cmd->ctx, "\tValid ROM table present");
else
- command_print(cmd_ctx, "\tROM table in legacy format");
+ command_print(cmd->ctx, "\tROM table in legacy format");
- dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
+ dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0);
}
}
return ERROR_COMMAND_SYNTAX_ERROR;
}
- return dap_info_command(CMD_CTX, &dap->ap[apsel]);
+ return dap_info_command(CMD, &dap->ap[apsel]);
}
COMMAND_HANDLER(dap_baseaddr_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
switch (reg) {
case MEM_AP_REG_CSW:
- ap->csw_default = 0; /* invalid, force write */
- retval = mem_ap_setup_csw(ap, value);
+ ap->csw_value = 0; /* invalid, in case write fails */
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->csw_value = value;
break;
case MEM_AP_REG_TAR:
ap->tar_valid = false; /* invalid, force write */
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