target/arm_adi_v5: fix sync CSW cache on apreg write

[openocd.git] / src / target / arm_adi_v5.c

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index d9f3bd74f86e209520f9bd864095ee110306cf51..e62ac07577acce79c56af03dcd8b04764a5b0ffe 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1738,8 +1738,10 @@ COMMAND_HANDLER(dap_apreg_command)
                COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
                switch (reg) {
                case MEM_AP_REG_CSW:
-                       ap->csw_default = 0;  /* invalid, force write */
-                       retval = mem_ap_setup_csw(ap, value);
+                       ap->csw_value = 0;  /* invalid, in case write fails */
+                       retval = dap_queue_ap_write(ap, reg, value);
+                       if (retval == ERROR_OK)
+                               ap->csw_value = value;
                        break;
                case MEM_AP_REG_TAR:
                        ap->tar_valid = false;  /* invalid, force write */