#include "config.h"
#endif
+#include "jtag/interface.h"
#include "arm.h"
#include "arm_adi_v5.h"
#include <helper/time_support.h>
/*****************************************************************************
* *
-* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
+* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address, bool addr_incr) *
* *
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
-int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
const uint8_t *pBuffer = buffer;
+ uint32_t incr_flag = CSW_ADDRINC_OFF;
count >>= 2;
wcount = count;
if (blocksize == 0)
blocksize = 1;
- retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ if (addr_incr)
+ incr_flag = CSW_ADDRINC_SINGLE;
+
+ retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag, address);
if (retval != ERROR_OK)
return retval;
for (writecount = 0; writecount < blocksize; writecount++) {
- retval = dap_queue_ap_write(dap, AP_REG_DRW,
- *(uint32_t *) ((void *) (buffer + 4 * writecount)));
+ uint32_t tmp;
+ tmp = buf_get_u32(buffer + 4 * writecount, 0, 32);
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, tmp);
if (retval != ERROR_OK)
break;
}
retval = dap_run(dap);
if (retval == ERROR_OK) {
wcount = wcount - blocksize;
- address = address + 4 * blocksize;
+ if (addr_incr)
+ address = address + 4 * blocksize;
buffer = buffer + 4 * blocksize;
} else
errorcount++;
* @param buffer where the words will be stored (in host byte order).
* @param count How many words to read.
* @param address Memory address from which to read words; all the
+ * @param addr_incr if true, increment the source address for each u32
* words must be readable by the currently selected MEM-AP.
*/
int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
- int count, uint32_t address)
+ int count, uint32_t address, bool addr_incr)
{
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
uint8_t *pBuffer = buffer;
+ uint32_t incr_flag = CSW_ADDRINC_OFF;
count >>= 2;
wcount = count;
if (blocksize == 0)
blocksize = 1;
- retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
+ if (addr_incr)
+ incr_flag = CSW_ADDRINC_SINGLE;
+
+ retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag,
address);
if (retval != ERROR_OK)
return retval;
return retval;
}
wcount = wcount - blocksize;
- address += 4 * blocksize;
+ if (addr_incr)
+ address += 4 * blocksize;
buffer += 4 * blocksize;
}
return mem_ap_read_buf_u16(swjdp, buffer, count, address);
}
+int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
+}
+
int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, int count, uint32_t address)
{
dap_ap_select(swjdp, ap);
- return mem_ap_read_buf_u32(swjdp, buffer, count, address);
+ return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
}
int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
const uint8_t *buffer, int count, uint32_t address)
{
dap_ap_select(swjdp, ap);
- return mem_ap_write_buf_u32(swjdp, buffer, count, address);
+ return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
+}
+
+int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
}
#define MDM_REG_STAT 0x00
/* we need to assert reset */
if (jtag_reset_config & RESET_HAS_SRST) {
/* default to asserting srst */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- jtag_add_reset(1, 1);
- else
- jtag_add_reset(0, 1);
+ adapter_assert_reset();
} else {
LOG_DEBUG("SRST not configured");
dap_ap_select(dap, 0);
LOG_DEBUG(" ");
- /* test for initialized low level jtag hardware
- * this always fails for stlink hardware
- */
- if (!dap->jtag_info) {
- LOG_DEBUG("No low level jtag hardware found");
- return ERROR_OK;
- }
-
/* JTAG-DP or SWJ-DP, in JTAG mode
* ... for SWD mode this is patched as part
* of link switchover
retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
+ if (retval != ERROR_OK)
+ return retval;
if ((devtype & 0xff) == type) {
*addr = component_base;
retval = ERROR_OK;
type = "Cortex-M3 FBP";
full = "(Flash Patch and Breakpoint)";
break;
+ case 0x00c:
+ type = "Cortex-M4 SCS";
+ full = "(System Control Space)";
+ break;
case 0x00d:
type = "CoreSight ETM11";
full = "(Embedded Trace)";
type = "Cortex-M3 ETM";
full = "(Embedded Trace)";
break;
+ case 0x925:
+ type = "Cortex-M4 ETM";
+ full = "(Embedded Trace)";
+ break;
case 0x930:
type = "Cortex-R4 ETM";
full = "(Embedded Trace)";
break;
+ case 0x9a1:
+ type = "Cortex-M4 TPUI";
+ full = "(Trace Port Interface Unit)";
+ break;
case 0xc08:
type = "Cortex-A8 Debug";
full = "(Debug Unit)";