* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
return ERROR_OK;
}
-static int arm946e_verify_pointer(struct command_context *cmd_ctx,
+static int arm946e_verify_pointer(struct command_invocation *cmd,
struct arm946e_common *arm946e)
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not an ARM946");
+ command_print(cmd->ctx, "target is not an ARM946");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
+/*
+ * Update cp15_control_reg, saved on debug_entry.
+ */
+static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
+{
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
+ | (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
+}
+
/*
* REVISIT: The "read_cp15" and "write_cp15" commands could hook up
* to eventual mrc() and mcr() routines ... the reg_addr values being
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm946e_write_memory(struct target *target, uint32_t address,
+int arm946e_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
/**
* Write memory
*/
- retval = arm7_9_write_memory(target, address, size, count, buffer);
+ retval = arm7_9_write_memory_opt(target, address, size, count, buffer);
if (retval != ERROR_OK)
return retval;
}
-int arm946e_read_memory(struct target *target, uint32_t address,
+int arm946e_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return ERROR_OK;
}
+COMMAND_HANDLER(arm946e_handle_cp15)
+{
+ /* one or two arguments, access a single register (write if second argument is given) */
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct target *target = get_current_target(CMD_CTX);
+
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ int retval = arm946e_verify_pointer(CMD, arm946e);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ uint32_t address;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+
+ if (CMD_ARGC == 1) {
+ uint32_t value;
+ retval = arm946e_read_cp15(target, address, &value);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ return retval;
+ }
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Return value in hex format */
+ command_print(CMD_CTX, "0x%08" PRIx32, value);
+ } else if (CMD_ARGC == 2) {
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
+ retval = arm946e_write_cp15(target, address, value);
+ if (retval != ERROR_OK) {
+ command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ return retval;
+ }
+ if (address == CP15_CTL)
+ arm946e_update_cp15_caches(target, value);
+ }
+
+ return ERROR_OK;
+}
-COMMAND_HANDLER(arm946e_handle_cp15_command)
+COMMAND_HANDLER(arm946e_handle_idcache)
{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm946e_common *arm946e = target_to_arm946(target);
- retval = arm946e_verify_pointer(CMD_CTX, arm946e);
+ retval = arm946e_verify_pointer(CMD, arm946e);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ bool icache = (strcmp(CMD_NAME, "icache") == 0);
+ uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
+ if (CMD_ARGC == 0) {
+ bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
+ && (arm946e->cp15_control_reg & 0x1);
+ if (csize == 0)
+ command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
+ else
+ command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s",
+ icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
return ERROR_OK;
}
- /* one or more argument, access a single register (write if second argument is given */
- if (CMD_ARGC >= 1) {
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ bool flush = false;
+ bool enable = false;
+ retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
+ if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
+ if (strcmp(CMD_ARGV[0], "flush") == 0) {
+ flush = true;
+ retval = ERROR_OK;
+ } else
+ return retval;
+ }
- if (CMD_ARGC == 1) {
- uint32_t value;
- retval = arm946e_read_cp15(target, address, &value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- return retval;
+ /* Do not invalidate or change state, if cache is absent */
+ if (csize == 0) {
+ command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- } else if (CMD_ARGC == 2) {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- retval = arm946e_write_cp15(target, address, value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- }
+ /* NOTE: flushing entire cache will not preserve lock-down cache regions */
+ if (icache) {
+ if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
+ retval = arm946e_invalidate_whole_icache(target);
+ } else {
+ if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
+ retval = arm946e_invalidate_whole_dcache(target);
}
+ if (retval != ERROR_OK || flush)
+ return retval;
+
+ uint32_t value;
+ retval = arm946e_read_cp15(target, CP15_CTL, &value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ uint32_t vnew = value;
+ uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
+ if (enable) {
+ if ((value & 0x1) == 0)
+ LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
+ vnew |= cmask;
+ } else
+ vnew &= ~cmask;
+
+ if (vnew == value)
+ return ERROR_OK;
+
+ retval = arm946e_write_cp15(target, CP15_CTL, vnew);
+ if (retval != ERROR_OK)
+ return retval;
+
+ arm946e_update_cp15_caches(target, vnew);
return ERROR_OK;
}
static const struct command_registration arm946e_exec_command_handlers[] = {
{
.name = "cp15",
- .handler = arm946e_handle_cp15_command,
+ .handler = arm946e_handle_cp15,
.mode = COMMAND_EXEC,
.usage = "regnum [value]",
- .help = "display/modify cp15 register",
+ .help = "read/modify cp15 register",
+ },
+ {
+ .name = "icache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "I-cache info and operations",
+ },
+ {
+ .name = "dcache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "D-cache info and operations",
},
COMMAND_REGISTRATION_DONE
};
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
/* .read_memory = arm7_9_read_memory, */
.read_memory = arm946e_read_memory,
.write_memory = arm946e_write_memory,
- .bulk_write_memory = arm7_9_bulk_write_memory,
-
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
Code Review / openocd.git / blobdiff