ARM: define two register utilities

[openocd.git] / src / target / arm926ejs.c

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 44afb2cea352b6754acba54c01bc43d815d1963e..7ecc7824a5ee59267fc0311524c62b712ab5ca08 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -565,18 +565,20 @@ int arm926ejs_soft_reset_halt(struct target *target)
        target->state = TARGET_HALTED;
 
        /* SVC, ARM state, IRQ and FIQ disabled */
-       buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+       uint32_t cpsr;
+
+       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr &= ~0xff;
+       cpsr |= 0xd3;
+       arm_set_cpsr(armv4_5, cpsr);
        armv4_5->cpsr->dirty = 1;
-       armv4_5->cpsr->valid = 1;
+       armv4_5->core_state = ARMV4_5_STATE_ARM;
 
        /* start fetching from 0x0 */
        buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
        armv4_5->core_cache->reg_list[15].dirty = 1;
        armv4_5->core_cache->reg_list[15].valid = 1;
 
-       armv4_5->core_mode = ARMV4_5_MODE_SVC;
-       armv4_5->core_state = ARMV4_5_STATE_ARM;
-
        arm926ejs_disable_mmu_caches(target, 1, 1, 1);
        arm926ejs->armv4_5_mmu.mmu_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;