* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008 Øyvind Harboe *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "log.h"
#include "arm7_9_common.h"
#include "breakpoints.h"
+#include "time_support.h"
#include <stdlib.h>
#include <string.h>
int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm7_9_reinit_embeddedice(target_t *target)
+
+static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
+ arm7_9->sw_breakpoints_added = 0;
+ arm7_9->wp0_used = 0;
+ arm7_9->wp1_used = arm7_9->wp1_used_default;
+ arm7_9->wp_available = arm7_9->wp_available_max;
- breakpoint_t *breakpoint = target->breakpoints;
+ return jtag_execute_queue();
+}
- arm7_9->wp_available = 2;
- arm7_9->wp0_used = 0;
- arm7_9->wp1_used = 0;
+/* set up embedded ice registers */
+static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
+{
+ if (arm7_9->sw_breakpoints_added)
+ {
+ return ERROR_OK;
+ }
+ if (arm7_9->wp_available < 1)
+ {
+ LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ arm7_9->wp_available--;
- /* mark all hardware breakpoints as unset */
- while (breakpoint)
+ /* pick a breakpoint unit */
+ if (!arm7_9->wp0_used)
{
- if (breakpoint->type == BKPT_HARD)
- {
- breakpoint->set = 0;
- }
- breakpoint = breakpoint->next;
+ arm7_9->sw_breakpoints_added=1;
+ arm7_9->wp0_used = 3;
+ } else if (!arm7_9->wp1_used)
+ {
+ arm7_9->sw_breakpoints_added=2;
+ arm7_9->wp1_used = 3;
+ }
+ else
+ {
+ LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
+ return ERROR_FAIL;
}
- if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
+ if (arm7_9->sw_breakpoints_added==1)
{
- arm7_9->sw_bkpts_enabled = 0;
- arm7_9_enable_sw_bkpts(target);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+ }
+ else if (arm7_9->sw_breakpoints_added==2)
+ {
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+ }
+ else
+ {
+ LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
+ return ERROR_FAIL;
}
- return ERROR_OK;
+ return jtag_execute_queue();
}
/* set things up after a reset / on startup */
int arm7_9_setup(target_t *target)
{
- /* a test-logic reset have occured
- * the EmbeddedICE registers have been reset
- * hardware breakpoints have been cleared
- */
- return arm7_9_reinit_embeddedice(target);
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+
+ return arm7_9_clear_watchpoints(arm7_9);
}
+
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
return ERROR_OK;
}
+/* we set up the breakpoint even if it is already set. Some action, e.g. reset
+ * might have erased the values in embedded ice
+ */
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ int retval=ERROR_OK;
if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
- if (arm7_9->force_hw_bkpts)
- breakpoint->type = BKPT_HARD;
-
- if (breakpoint->set)
- {
- LOG_WARNING("breakpoint already set");
- return ERROR_OK;
- }
-
if (breakpoint->type == BKPT_HARD)
{
/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
- if (!arm7_9->wp0_used)
+ if (breakpoint->set==1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-
- jtag_execute_queue();
- arm7_9->wp0_used = 1;
- breakpoint->set = 1;
}
- else if (!arm7_9->wp1_used)
+ else if (breakpoint->set==2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-
- jtag_execute_queue();
- arm7_9->wp1_used = 1;
- breakpoint->set = 2;
}
else
{
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
+
+ retval=jtag_execute_queue();
}
else if (breakpoint->type == BKPT_SOFT)
{
+ if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+ return retval;
+
+ /* did we already set this breakpoint? */
+ if (breakpoint->set)
+ return ERROR_OK;
+
if (breakpoint->length == 4)
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
- target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
+ if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
- target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
- target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
+ if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
+ {
+ return retval;
+ }
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
+ {
+ return retval;
+ }
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
breakpoint->set = 1;
}
- return ERROR_OK;
+ return retval;
}
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval = ERROR_OK;
+
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (!breakpoint->set)
{
LOG_WARNING("breakpoint not set");
if (breakpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
arm7_9->wp0_used = 0;
}
else if (breakpoint->set == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
arm7_9->wp1_used = 0;
}
+ retval = jtag_execute_queue();
breakpoint->set = 0;
}
else
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->arm_bkpt)
- target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
- target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
+ if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
if (current_instr==arm7_9->thumb_bkpt)
- target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+ if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+ {
+ return retval;
+ }
}
breakpoint->set = 0;
}
- return ERROR_OK;
+ return retval;
}
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_TARGET_NOT_HALTED;
}
- if (arm7_9->force_hw_bkpts)
- {
- LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
- breakpoint->type = BKPT_HARD;
- }
-
- if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
+ if (arm7_9->breakpoint_count==0)
{
- LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ /* make sure we don't have any dangling breakpoints. This is vital upon
+ * GDB connect/disconnect
+ */
+ arm7_9_clear_watchpoints(arm7_9);
}
if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
}
if (breakpoint->type == BKPT_HARD)
+ {
arm7_9->wp_available--;
- return ERROR_OK;
+ if (!arm7_9->wp0_used)
+ {
+ arm7_9->wp0_used = 1;
+ breakpoint->set = 1;
+ }
+ else if (!arm7_9->wp1_used)
+ {
+ arm7_9->wp1_used = 1;
+ breakpoint->set = 2;
+ }
+ else
+ {
+ LOG_ERROR("BUG: no hardware comparator available");
+ }
+ }
+
+
+ arm7_9->breakpoint_count++;
+
+ return arm7_9_set_breakpoint(target, breakpoint);
}
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- if (breakpoint->set)
+ if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
- arm7_9_unset_breakpoint(target, breakpoint);
+ return retval;
}
if (breakpoint->type == BKPT_HARD)
arm7_9->wp_available++;
+ arm7_9->breakpoint_count--;
+ if (arm7_9->breakpoint_count==0)
+ {
+ /* make sure we don't have any dangling breakpoints */
+ if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+
return ERROR_OK;
}
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int rw_mask = 1;
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
watchpoint->set = 1;
arm7_9->wp0_used = 2;
}
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
watchpoint->set = 2;
arm7_9->wp1_used = 2;
}
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (watchpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->wp0_used = 0;
}
else if (watchpoint->set == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
- jtag_execute_queue();
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->wp1_used = 0;
}
watchpoint->set = 0;
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (watchpoint->set)
{
- arm7_9_unset_watchpoint(target, watchpoint);
+ if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
}
arm7_9->wp_available++;
return ERROR_OK;
}
-int arm7_9_enable_sw_bkpts(struct target_s *target)
-{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- int retval;
- if (arm7_9->sw_bkpts_enabled)
- return ERROR_OK;
- if (arm7_9->wp_available < 1)
- {
- LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
- arm7_9->wp_available--;
-
- if (!arm7_9->wp0_used)
- {
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
- arm7_9->sw_bkpts_enabled = 1;
- arm7_9->wp0_used = 3;
- }
- else if (!arm7_9->wp1_used)
- {
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
- embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
- arm7_9->sw_bkpts_enabled = 2;
- arm7_9->wp1_used = 3;
- }
- else
- {
- LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
- return ERROR_FAIL;
- }
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
- return ERROR_FAIL;
- };
-
- return ERROR_OK;
-}
-
-int arm7_9_disable_sw_bkpts(struct target_s *target)
-{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
- if (!arm7_9->sw_bkpts_enabled)
- return ERROR_OK;
-
- if (arm7_9->sw_bkpts_enabled == 1)
- {
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
- arm7_9->sw_bkpts_enabled = 0;
- arm7_9->wp0_used = 0;
- arm7_9->wp_available++;
- }
- else if (arm7_9->sw_bkpts_enabled == 2)
- {
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
- arm7_9->sw_bkpts_enabled = 0;
- arm7_9->wp1_used = 0;
- arm7_9->wp_available++;
- }
-
- return ERROR_OK;
-}
int arm7_9_execute_sys_speed(struct target_s *target)
{
- int timeout;
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
- for (timeout=0; timeout<50; timeout++)
+ long long then=timeval_ms();
+ int timeout;
+ while (!(timeout=((timeval_ms()-then)>1000)))
{
/* read debug status register */
embeddedice_read_reg(dbg_stat);
if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
&& (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
break;
- usleep(100000);
+ if (debug_level>=3)
+ {
+ alive_sleep(100);
+ } else
+ {
+ keep_alive();
+ }
}
- if (timeout == 50)
+ if (timeout)
{
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
return ERROR_TARGET_TIMEOUT;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 *data;
- int i;
+ int i, retval = ERROR_OK;
data = malloc(size * (sizeof(u32)));
- embeddedice_receive(jtag_info, data, size);
+ retval = embeddedice_receive(jtag_info, data, size);
for (i = 0; i < size; i++)
{
free(data);
- return ERROR_OK;
+ return retval;
}
int arm7_9_handle_target_request(void *priv)
{
+ int retval = ERROR_OK;
target_t *target = priv;
if (!target->type->examined)
return ERROR_OK;
{
/* read DCC control register */
embeddedice_read_reg(dcc_control);
- jtag_execute_queue();
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
/* check W bit */
if (buf_get_u32(dcc_control->value, 1, 1) == 1)
{
u32 request;
- embeddedice_receive(jtag_info, &request, 1);
- target_request(target, request);
+ if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_request(target, request)) != ERROR_OK)
+ {
+ return retval;
+ }
}
}
}
}
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
if (target->state == TARGET_DEBUG_RUNNING)
{
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
if (target->state != TARGET_HALTED)
{
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s",
+ Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
if (!(jtag_reset_config & RESET_HAS_SRST))
{
armv4_5_invalidate_core_regs(target);
+ if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+ {
+ /* debug entry was already prepared in arm7_9_assert_reset() */
+ target->debug_reason = DBG_REASON_DBGRQ;
+ }
+
return ERROR_OK;
}
int arm7_9_deassert_reset(target_t *target)
{
- LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+ int retval=ERROR_OK;
+ LOG_DEBUG("target->state: %s",
+ Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+
/* deassert reset lines */
jtag_add_reset(0, 0);
- return ERROR_OK;
+ if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+ {
+ LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
+ /* set up embedded ice registers again */
+ if ((retval=target->type->examine(target))!=ERROR_OK)
+ return retval;
+
+ if ((retval=target_poll(target))!=ERROR_OK)
+ {
+ return retval;
+ }
+
+ if ((retval=target_halt(target))!=ERROR_OK)
+ {
+ return retval;
+ }
+
+ }
+ return retval;
}
int arm7_9_clear_halt(target_t *target)
if ((retval=target_halt(target))!=ERROR_OK)
return retval;
- for (i=0; i<10; i++)
+ long long then=timeval_ms();
+ int timeout;
+ while (!(timeout=((timeval_ms()-then)>1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
break;
embeddedice_read_reg(dbg_stat);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
- /* do not eat all CPU, time out after 1 se*/
- usleep(100*1000);
-
+ if (debug_level>=3)
+ {
+ alive_sleep(100);
+ } else
+ {
+ keep_alive();
+ }
}
- if (i==10)
+ if (timeout)
{
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- arm7_9_clear_halt(target);
+ if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
/* if the target is in Thumb state, change to ARM state */
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
}
/* all register content is now invalid */
- armv4_5_invalidate_core_regs(target);
+ if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
+ {
+ return retval;
+ }
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
}
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
int arm7_9_halt(target_t *target)
{
+ if (target->state==TARGET_RESET)
+ {
+ LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
+ return ERROR_OK;
+ }
+
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s",
+ Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
if (target->state == TARGET_HALTED)
{
return ERROR_OK;
}
- if (target->state == TARGET_UNKNOWN)
- {
- LOG_WARNING("target was in unknown state when halt was requested");
- }
-
- if (target->state == TARGET_RESET)
- {
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
- {
- LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
- return ERROR_TARGET_FAILURE;
- }
- else
- {
- /* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in arm7_9_assert_reset()
- */
- target->debug_reason = DBG_REASON_DBGRQ;
-
- return ERROR_OK;
- }
+ if (target->state == TARGET_UNKNOWN)
+ {
+ LOG_WARNING("target was in unknown state when halt was requested");
}
if (arm7_9->use_dbgrq)
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- arm7_9_clear_halt(target);
+ if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
{
u32 spsr;
arm7_9->read_xpsr(target, &spsr, 1);
- jtag_execute_queue();
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
/* set any pending breakpoints */
while (breakpoint)
{
- if (breakpoint->set == 0)
- arm7_9_set_breakpoint(target, breakpoint);
+ arm7_9_set_breakpoint(target, breakpoint);
breakpoint = breakpoint->next;
}
}
-void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
-{
- breakpoint_t *breakpoint = target->breakpoints;
- watchpoint_t *watchpoint = target->watchpoints;
-
- /* set any pending breakpoints */
- while (breakpoint)
- {
- if (breakpoint->set != 0)
- arm7_9_unset_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-
- while (watchpoint)
- {
- if (watchpoint->set != 0)
- arm7_9_unset_watchpoint(target, watchpoint);
- watchpoint = watchpoint->next;
- }
-}
int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- int err;
+ int err, retval = ERROR_OK;
LOG_DEBUG("-");
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
- arm7_9_unset_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_DEBUG("enable single-step");
arm7_9->enable_single_step(target);
target->debug_reason = DBG_REASON_SINGLESTEP;
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
arm7_9->branch_resume(target);
if (err != ERROR_OK)
{
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
target->state = TARGET_UNKNOWN;
return err;
}
LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
}
}
arm7_9_enable_breakpoints(target);
arm7_9_enable_watchpoints(target);
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
{
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
- arm7_9_restart_core(target);
+ if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
+ {
+ return retval;
+ }
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RUNNING;
- target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
else
{
target->state = TARGET_DEBUG_RUNNING;
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
}
LOG_DEBUG("target resumed");
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
breakpoint_t *breakpoint = NULL;
- int err;
+ int err, retval;
if (target->state != TARGET_HALTED)
{
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
- arm7_9_unset_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
target->debug_reason = DBG_REASON_SINGLESTEP;
- arm7_9_restore_context(target);
+ if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+ {
+ return retval;
+ }
arm7_9->enable_single_step(target);
return ERROR_FAIL;
}
- target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
+ {
+ return retval;
+ }
err = arm7_9_execute_sys_speed(target);
arm7_9->disable_single_step(target);
target->state = TARGET_UNKNOWN;
} else {
arm7_9_debug_entry(target);
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
LOG_DEBUG("target stepped");
}
if (breakpoint)
- arm7_9_set_breakpoint(target, breakpoint);
+ if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
+ {
+ return retval;
+ }
return err;
reg[0] = address;
arm7_9->write_core_regs(target, 0x1, reg);
+ int j=0;
+
switch (size)
{
case 4:
/* advance buffer, count number of accesses */
buffer += thisrun_accesses * 4;
num_accesses += thisrun_accesses;
+
+ if ((j++%1024)==0)
+ {
+ keep_alive();
+ }
}
break;
case 2:
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
+
}
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
/* advance buffer, count number of accesses */
buffer += thisrun_accesses * 2;
num_accesses += thisrun_accesses;
+
+ if ((j++%1024)==0)
+ {
+ keep_alive();
+ }
}
break;
case 1:
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
}
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
/* advance buffer, count number of accesses */
buffer += thisrun_accesses * 1;
num_accesses += thisrun_accesses;
+
+ if ((j++%1024)==0)
+ {
+ keep_alive();
+ }
}
break;
default:
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
num_accesses += thisrun_accesses;
}
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
}
num_accesses += thisrun_accesses;
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
- arm7_9_execute_fast_sys_speed(target);
+ retval = arm7_9_execute_fast_sys_speed(target);
else
- arm7_9_execute_sys_speed(target);
+ retval = arm7_9_execute_sys_speed(target);
+ if(retval != ERROR_OK)
+ {
+ return retval;
+ }
+
}
num_accesses += thisrun_accesses;
return ERROR_OK;
}
+static int dcc_count;
+static u8 *dcc_buffer;
+
+
+static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
+{
+ int retval = ERROR_OK;
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+
+ if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+ return retval;
+
+ int little=target->endianness==TARGET_LITTLE_ENDIAN;
+ int count=dcc_count;
+ u8 *buffer=dcc_buffer;
+ if (count>2)
+ {
+ /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+ core function repeated.
+ */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer+=4;
+
+ embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+ u8 reg_addr = ice_reg->addr & 0x1f;
+ int chain_pos = ice_reg->jtag_info->chain_pos;
+
+ embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
+ buffer += (count-2)*4;
+
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ } else
+ {
+ int i;
+ for (i = 0; i < count; i++)
+ {
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ }
+
+ if((retval = target_halt(target))!= ERROR_OK)
+ {
+ return retval;
+ }
+ return target_wait_state(target, TARGET_HALTED, 500);
+}
+
+
static const u32 dcc_code[] =
{
/* MRC TST BNE MRC STR B */
0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
};
+int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
+
+
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
+ int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- enum armv4_5_state core_state = armv4_5->core_state;
- u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
- u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
- u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
int i;
if (!arm7_9->dcc_downloads)
}
/* write DCC code to working area */
- target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
+ if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
+ {
+ return retval;
+ }
}
- buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
- armv4_5->core_cache->reg_list[0].valid = 1;
- armv4_5->core_cache->reg_list[0].dirty = 1;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ armv4_5_algorithm_t armv4_5_info;
+ reg_param_t reg_params[1];
- arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
+ armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_state = ARMV4_5_STATE_ARM;
- int little=target->endianness==TARGET_LITTLE_ENDIAN;
- if (count>2)
- {
- /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
- core function repeated.
- */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
- buffer+=4;
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
- embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
- u8 reg_addr = ice_reg->addr & 0x1f;
- int chain_pos = ice_reg->jtag_info->chain_pos;
+ buf_set_u32(reg_params[0].value, 0, 32, address);
- embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
- buffer += (count-2)*4;
+ //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
+ // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
+ dcc_count=count;
+ dcc_buffer=buffer;
+ retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
+ arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
- } else
+ if (retval==ERROR_OK)
{
- for (i = 0; i < count; i++)
+ u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
+ if (endaddress!=(address+count*4))
{
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
- buffer += 4;
+ LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
+ retval=ERROR_FAIL;
}
}
- target_halt(target);
-
- for (i=0; i<100; i++)
- {
- target_poll(target);
- if (target->state == TARGET_HALTED)
- break;
- usleep(1000); /* sleep 1ms */
- }
- if (i == 100)
- {
- LOG_ERROR("bulk write timed out, target not halted");
- return ERROR_TARGET_TIMEOUT;
- }
-
- /* restore target state */
- buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
- armv4_5->core_cache->reg_list[0].valid = 1;
- armv4_5->core_cache->reg_list[0].dirty = 1;
- buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
- armv4_5->core_cache->reg_list[1].valid = 1;
- armv4_5->core_cache->reg_list[1].dirty = 1;
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
- armv4_5->core_cache->reg_list[15].valid = 1;
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_state = core_state;
+ destroy_reg_param(®_params[0]);
- return ERROR_OK;
+ return retval;
}
int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
- target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
+ {
+ if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
+ {
+ return retval;
+ }
+ }
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
- target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
+ if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
+ {
+ return retval;
+ }
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
- register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
- register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
mode = strtoul(args[1], NULL, 0);
value = strtoul(args[2], NULL, 0);
- arm7_9_write_core_reg(target, num, mode, value);
-
- return ERROR_OK;
-}
-
-int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
-
- if (target->state != TARGET_HALTED)
- {
- LOG_ERROR("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
- return ERROR_OK;
- }
-
- if (argc == 0)
- {
- command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
- return ERROR_OK;
- }
-
- if (strcmp("enable", args[0]) == 0)
- {
- if (arm7_9->sw_bkpts_use_wp)
- {
- arm7_9_enable_sw_bkpts(target);
- }
- else
- {
- arm7_9->sw_bkpts_enabled = 1;
- }
- }
- else if (strcmp("disable", args[0]) == 0)
- {
- if (arm7_9->sw_bkpts_use_wp)
- {
- arm7_9_disable_sw_bkpts(target);
- }
- else
- {
- arm7_9->sw_bkpts_enabled = 0;
- }
- }
- else
- {
- command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
- }
-
- command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
+ return arm7_9_write_core_reg(target, num, mode, value);
- return ERROR_OK;
}
-int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
-
- if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
- return ERROR_OK;
- }
-
- if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
- {
- arm7_9->force_hw_bkpts = 1;
- if (arm7_9->sw_bkpts_use_wp)
- {
- arm7_9_disable_sw_bkpts(target);
- }
- }
- else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
- {
- arm7_9->force_hw_bkpts = 0;
- }
- else
- {
- command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
- }
-
- command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
-
- return ERROR_OK;
-}
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
{
+ int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
- arm_jtag_setup_connection(&arm7_9->jtag_info);
- arm7_9->wp_available = 2;
+ if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
+ arm7_9->wp_available_max = 2;
+ arm7_9->sw_breakpoints_added = 0;
+ arm7_9->breakpoint_count = 0;
arm7_9->wp0_used = 0;
arm7_9->wp1_used = 0;
- arm7_9->force_hw_bkpts = 0;
+ arm7_9->wp1_used_default = 0;
arm7_9->use_dbgrq = 0;
arm7_9->etm_ctx = NULL;
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
- armv4_5_init_arch_info(target, armv4_5);
+ if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+ {
+ return retval;
+ }
- target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
+ if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+ {
+ return retval;
+ }
return ERROR_OK;
}
Code Review / openocd.git / blobdiff