target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if (verify != arm7_9->arm_bkpt)
{
- LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
+ LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
}
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if (verify != arm7_9->thumb_bkpt)
{
- LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
+ LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
}
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
+ if (arm7_9->need_bypass_before_restart) {
+ arm7_9->need_bypass_before_restart = 0;
+ arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ }
arm_jtag_set_instr(jtag_info, 0x4, NULL);
for (timeout=0; timeout<50; timeout++)
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
+ if (arm7_9->need_bypass_before_restart) {
+ arm7_9->need_bypass_before_restart = 0;
+ arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ }
arm_jtag_set_instr(jtag_info, 0x4, NULL);
if (!set)
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
int check_pc=0;
- target->state = TARGET_HALTED;
-
if (target->state == TARGET_RESET)
{
- if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+ if (target->reset_halt)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
{
}
}
+ target->state = TARGET_HALTED;
+
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
u32 t=*((u32 *)reg->value);
if (t!=0)
{
- LOG_ERROR("PC was not 0. Does this target does target need srst_pulls_trst?");
+ LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
}
return ERROR_FAIL;
}
- if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+ if (target->reset_halt)
{
/*
* Some targets do not support communication while SRST is asserted. We need to
else
{
/* program watchpoint unit to match on reset vector address */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
}
}
*/
if (arm7_9->wp0_used)
{
+ if (arm7_9->debug_entry_from_reset)
+ {
+ embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
+ }
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
else
{
/* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in arm7_9_prepare_reset_halt()
+ * debug entry was already prepared in arm7_9_assert_reset()
*/
target->debug_reason = DBG_REASON_DBGRQ;
{
/* program EmbeddedICE Debug Control Register to assert DBGRQ
*/
- buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
- embeddedice_store_reg(dbg_ctrl);
+ if (arm7_9->set_special_dbgrq) {
+ arm7_9->set_special_dbgrq(target);
+ } else {
+ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
+ embeddedice_store_reg(dbg_ctrl);
+ }
}
else
{
*/
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
}
target->debug_reason = DBG_REASON_DBGRQ;
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
+ if (arm7_9->need_bypass_before_restart) {
+ arm7_9->need_bypass_before_restart = 0;
+ arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ }
arm_jtag_set_instr(jtag_info, 0x4, NULL);
jtag_add_runtest(1, TAP_RTI);
* - comparator 0 matches any address, as long as rangein is low */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
}
void arm7_9_disable_eice_step(target_t *target)
arm7_9->fast_memory_access = fast_and_dangerous;
arm7_9->dcc_downloads = fast_and_dangerous;
-
+
+ arm7_9->need_bypass_before_restart = 0;
+
armv4_5->arch_info = arm7_9;
armv4_5->read_core_reg = arm7_9_read_core_reg;
armv4_5->write_core_reg = arm7_9_write_core_reg;