- jtag_khz/speed are now single parameter only. These are used

[openocd.git] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ad184f214307589006e91df6230b29013b35f0d7..563f470159682725ed59be87f5980a19c1e6d63a 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -185,7 +185,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
                        if (verify != arm7_9->arm_bkpt)
                        {
-                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
+                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
@@ -200,7 +200,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
                        if (verify != arm7_9->thumb_bkpt)
                        {
-                               LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
+                               LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
@@ -702,11 +702,9 @@ int arm7_9_poll(target_t *target)
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
                        int check_pc=0;
-                       target->state = TARGET_HALTED;
-                       
                        if (target->state == TARGET_RESET)
                        {
-                               if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+                               if (target->reset_halt)
                                {
                                        if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
                                        {
@@ -715,6 +713,8 @@ int arm7_9_poll(target_t *target)
                                }
                        }
                        
+                       target->state = TARGET_HALTED;
+                       
                        if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
                                return retval;
                        
@@ -724,7 +724,7 @@ int arm7_9_poll(target_t *target)
                                u32 t=*((u32 *)reg->value);
                                if (t!=0)
                                {
-                                       LOG_ERROR("PC was not 0. Does this target does target need srst_pulls_trst?");
+                                       LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
                                }
                        }
                        
@@ -772,7 +772,7 @@ int arm7_9_assert_reset(target_t *target)
                return ERROR_FAIL;
        }
 
-       if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+       if (target->reset_halt)
        {
                /*
                 * Some targets do not support communication while SRST is asserted. We need to
@@ -789,10 +789,11 @@ int arm7_9_assert_reset(target_t *target)
                else
                {
                        /* program watchpoint unit to match on reset vector address */
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
                        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
-                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
-                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
-                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                }
        }
 
@@ -855,6 +856,10 @@ int arm7_9_clear_halt(target_t *target)
                         */
                        if (arm7_9->wp0_used)
                        {
+                               if (arm7_9->debug_entry_from_reset)
+                               {
+                                       embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
+                               }
                                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
                                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
                                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
@@ -980,7 +985,7 @@ int arm7_9_halt(target_t *target)
                else
                {
                        /* we came here in a reset_halt or reset_init sequence
-                        * debug entry was already prepared in arm7_9_prepare_reset_halt()
+                        * debug entry was already prepared in arm7_9_assert_reset()
                         */
                        target->debug_reason = DBG_REASON_DBGRQ;
                        
@@ -1005,8 +1010,8 @@ int arm7_9_halt(target_t *target)
                 */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
        }
 
        target->debug_reason = DBG_REASON_DBGRQ;
@@ -1590,13 +1595,13 @@ void arm7_9_enable_eice_step(target_t *target)
        * - comparator 0 matches any address, as long as rangein is low */
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
-       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
-       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
+       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
+       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 }
 
 void arm7_9_disable_eice_step(target_t *target)