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ARM7/ARM9: help/usage updates
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 928923dfbe1c81d3239a946d53b897b137b60a06..2f4c408ce8124cda4547acb14535d3eb58b144bb 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -39,6 +39,7 @@
 #include "arm_semihosting.h"
 #include "algorithm.h"
 #include "register.h"
+#include "armv4_5.h"
 
 
 /**
@@ -888,34 +889,11 @@ int arm7_9_poll(struct target *target)
                }
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
-                       int check_pc = 0;
-                       if (target->state == TARGET_RESET)
-                       {
-                               if (target->reset_halt)
-                               {
-                                       enum reset_types jtag_reset_config = jtag_get_reset_config();
-                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
-                                       {
-                                               check_pc = 1;
-                                       }
-                               }
-                       }
-
                        target->state = TARGET_HALTED;
 
                        if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
                                return retval;
 
-                       if (check_pc)
-                       {
-                               struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
-                               uint32_t t=*((uint32_t *)reg->value);
-                               if (t != 0)
-                               {
-                                       LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
-                               }
-                       }
-
                        if (arm_semihosting(target, &retval) != 0)
                                return retval;
 
@@ -1582,7 +1560,7 @@ int arm7_9_restore_context(struct target *target)
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *reg;
        struct arm_reg *reg_arch_info;
-       enum armv4_5_mode current_mode = armv4_5->core_mode;
+       enum arm_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
        int mode_change;
@@ -2093,7 +2071,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 }
 
 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode)
+               int num, enum arm_mode mode)
 {
        uint32_t* reg_p[16];
        uint32_t value;
@@ -2157,7 +2135,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode, uint32_t value)
+               int num, enum arm_mode mode, uint32_t value)
 {
        uint32_t reg[16];
        struct arm_reg *areg = r->arch_info;
@@ -2361,10 +2339,6 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                }
                        }
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
-                       break;
        }
 
        if (!is_arm_mode(armv4_5->core_mode))
@@ -2545,10 +2519,6 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                                num_accesses += thisrun_accesses;
                        }
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
-                       break;
        }
 
        /* Re-Set DBGACK */
@@ -2651,14 +2621,6 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-extern int armv4_5_run_algorithm_inner(struct target *target,
-       int num_mem_params, struct mem_param *mem_params,
-       int num_reg_params, struct reg_param *reg_params,
-       uint32_t entry_point, uint32_t exit_point,
-       int timeout_ms, void *arch_info,
-       int (*run_it)(struct target *target, uint32_t exit_point,
-                       int timeout_ms, void *arch_info));
-
 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        int retval;
@@ -2693,10 +2655,10 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
                }
        }
 
-       struct armv4_5_algorithm armv4_5_info;
+       struct arm_algorithm armv4_5_info;
        struct reg_param reg_params[1];
 
-       armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+       armv4_5_info.common_magic = ARM_COMMON_MAGIC;
        armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -2835,7 +2797,12 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 
                COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
 
-               /* TODO: support other methods if vector catch is unavailable */
+               if (!target_was_examined(target))
+               {
+                       LOG_ERROR("Target not examined yet");
+                       return ERROR_FAIL;
+               }
+
                if (arm7_9->has_vector_catch) {
                        struct reg *vector_catch = &arm7_9->eice_cache
                                        ->reg_list[EICE_VEC_CATCH];
@@ -2844,14 +2811,17 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
                                embeddedice_read_reg(vector_catch);
                        buf_set_u32(vector_catch->value, 2, 1, semihosting);
                        embeddedice_store_reg(vector_catch);
+               } else {
+                       /* TODO: allow optional high vectors and/or BKPT_HARD */
+                       if (semihosting)
+                               breakpoint_add(target, 8, 4, BKPT_SOFT);
+                       else
+                               breakpoint_remove(target, 8); 
+               }
 
-                       /* FIXME never let that "catch" be dropped! */
-
-                       arm7_9->armv4_5_common.is_semihosting = semihosting;
+               /* FIXME never let that "catch" be dropped! */
+               arm7_9->armv4_5_common.is_semihosting = semihosting;
 
-               } else if (semihosting) {
-                       command_print(CMD_CTX, "vector catch unavailable");
-               }
        }
 
        command_print(CMD_CTX, "semihosting is %s",
@@ -2883,7 +2853,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
-       if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+       retval = arm_init_arch_info(target, armv4_5);
+       if (retval != ERROR_OK)
                return retval;
 
        return target_register_timer_callback(arm7_9_handle_target_request,
@@ -2893,32 +2864,32 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 static const struct command_registration arm7_9_any_command_handlers[] = {
        {
                "dbgrq",
-               .handler = &handle_arm7_9_dbgrq_command,
+               .handler = handle_arm7_9_dbgrq_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable|disable>",
+               .usage = "['enable'|'disable']",
                .help = "use EmbeddedICE dbgrq instead of breakpoint "
                        "for target halt requests",
        },
        {
                "fast_memory_access",
-               .handler = &handle_arm7_9_fast_memory_access_command,
+               .handler = handle_arm7_9_fast_memory_access_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable|disable>",
+               .usage = "['enable'|'disable']",
                .help = "use fast memory accesses instead of slower "
                        "but potentially safer accesses",
        },
        {
                "dcc_downloads",
-               .handler = &handle_arm7_9_dcc_downloads_command,
+               .handler = handle_arm7_9_dcc_downloads_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable | disable>",
+               .usage = "['enable'|'disable']",
                .help = "use DCC downloads for larger memory writes",
        },
        {
                "semihosting",
-               .handler = &handle_arm7_9_semihosting_command,
+               .handler = handle_arm7_9_semihosting_command,
                .mode = COMMAND_EXEC,
-               .usage = "<enable | disable>",
+               .usage = "['enable'|'disable']",
                .help = "activate support for semihosting operations",
        },
        COMMAND_REGISTRATION_DONE
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