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ARM7/ARM9: help/usage updates
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 7318b5f36867a8332af2e7cf8d86e36d4ccb9c9e..2f4c408ce8124cda4547acb14535d3eb58b144bb 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -39,6 +39,7 @@
 #include "arm_semihosting.h"
 #include "algorithm.h"
 #include "register.h"
+#include "armv4_5.h"
 
 
 /**
@@ -888,34 +889,11 @@ int arm7_9_poll(struct target *target)
                }
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
-                       int check_pc = 0;
-                       if (target->state == TARGET_RESET)
-                       {
-                               if (target->reset_halt)
-                               {
-                                       enum reset_types jtag_reset_config = jtag_get_reset_config();
-                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
-                                       {
-                                               check_pc = 1;
-                                       }
-                               }
-                       }
-
                        target->state = TARGET_HALTED;
 
                        if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
                                return retval;
 
-                       if (check_pc)
-                       {
-                               struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
-                               uint32_t t=*((uint32_t *)reg->value);
-                               if (t != 0)
-                               {
-                                       LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
-                               }
-                       }
-
                        if (arm_semihosting(target, &retval) != 0)
                                return retval;
 
@@ -1211,7 +1189,7 @@ int arm7_9_soft_reset_halt(struct target *target)
                uint32_t r0_thumb, pc_thumb;
                LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
                /* Entered debug from Thumb mode */
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               armv4_5->core_state = ARM_STATE_THUMB;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
        }
 
@@ -1373,7 +1351,7 @@ static int arm7_9_debug_entry(struct target *target)
        {
                LOG_DEBUG("target entered debug from Thumb state");
                /* Entered debug from Thumb mode */
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               armv4_5->core_state = ARM_STATE_THUMB;
                cpsr_mask = 1 << 5;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
                LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
@@ -1385,13 +1363,13 @@ static int arm7_9_debug_entry(struct target *target)
                 * B.7.3 for the reverse.  That'd be the bare minimum...
                 */
                LOG_DEBUG("target entered debug from Jazelle state");
-               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+               armv4_5->core_state = ARM_STATE_JAZELLE;
                cpsr_mask = 1 << 24;
                LOG_ERROR("Jazelle debug entry -- BROKEN!");
        } else {
                LOG_DEBUG("target entered debug from ARM state");
                /* Entered debug from ARM mode */
-               armv4_5->core_state = ARMV4_5_STATE_ARM;
+               armv4_5->core_state = ARM_STATE_ARM;
        }
 
        for (i = 0; i < 16; i++)
@@ -1419,21 +1397,21 @@ static int arm7_9_debug_entry(struct target *target)
        LOG_DEBUG("target entered debug state in %s mode",
                         arm_mode_name(armv4_5->core_mode));
 
-       if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                LOG_DEBUG("thumb state, applying fixups");
                context[0] = r0_thumb;
                context[15] = pc_thumb;
-       } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       } else if (armv4_5->core_state == ARM_STATE_ARM)
        {
                /* adjust value stored by STM */
                context[15] -= 3 * 4;
        }
 
        if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
-               context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+               context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
        else
-               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
 
        for (i = 0; i <= 15; i++)
        {
@@ -1582,7 +1560,7 @@ int arm7_9_restore_context(struct target *target)
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *reg;
        struct arm_reg *reg_arch_info;
-       enum armv4_5_mode current_mode = armv4_5->core_mode;
+       enum arm_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
        int mode_change;
@@ -1622,10 +1600,10 @@ int arm7_9_restore_context(struct target *target)
                                {
                                        dirty = 1;
                                        LOG_DEBUG("examining dirty reg: %s", reg->name);
-                                       if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+                                       if ((reg_arch_info->mode != ARM_MODE_ANY)
                                                && (reg_arch_info->mode != current_mode)
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+                                               && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+                                               && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
                                        {
                                                mode_change = 1;
                                                LOG_DEBUG("require mode change");
@@ -1684,7 +1662,7 @@ int arm7_9_restore_context(struct target *target)
 
                        reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
                        reg_arch_info = reg->arch_info;
-                       if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+                       if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
                        {
                                LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -1846,9 +1824,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                                return retval;
                        }
 
-                       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+                       if (armv4_5->core_state == ARM_STATE_ARM)
                                arm7_9->branch_resume(target);
-                       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+                       else if (armv4_5->core_state == ARM_STATE_THUMB)
                        {
                                arm7_9->branch_resume_thumb(target);
                        }
@@ -1895,11 +1873,11 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                return retval;
        }
 
-       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       if (armv4_5->core_state == ARM_STATE_ARM)
        {
                arm7_9->branch_resume(target);
        }
-       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       else if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                arm7_9->branch_resume_thumb(target);
        }
@@ -2046,11 +2024,11 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 
        arm7_9->enable_single_step(target, next_pc);
 
-       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       if (armv4_5->core_state == ARM_STATE_ARM)
        {
                arm7_9->branch_resume(target);
        }
-       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       else if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                arm7_9->branch_resume_thumb(target);
        }
@@ -2093,7 +2071,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 }
 
 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode)
+               int num, enum arm_mode mode)
 {
        uint32_t* reg_p[16];
        uint32_t value;
@@ -2107,9 +2085,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))
+                       && (areg->mode != ARM_MODE_ANY))
        {
                uint32_t tmp_cpsr;
 
@@ -2132,7 +2110,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+               arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
        }
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2144,9 +2122,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        r->dirty = 0;
        buf_set_u32(r->value, 0, 32, value);
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2157,7 +2135,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode, uint32_t value)
+               int num, enum arm_mode mode, uint32_t value)
 {
        uint32_t reg[16];
        struct arm_reg *areg = r->arch_info;
@@ -2169,9 +2147,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
@@ -2193,7 +2171,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+               int spsr = (areg->mode != ARM_MODE_ANY);
 
                /* if we're writing the CPSR, mask the T bit */
                if (!spsr)
@@ -2205,9 +2183,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        r->valid = 1;
        r->dirty = 0;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2361,10 +2339,6 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                }
                        }
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
-                       break;
        }
 
        if (!is_arm_mode(armv4_5->core_mode))
@@ -2383,7 +2357,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2545,10 +2519,6 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                                num_accesses += thisrun_accesses;
                        }
                        break;
-               default:
-                       LOG_ERROR("BUG: we shouldn't get here");
-                       exit(-1);
-                       break;
        }
 
        /* Re-Set DBGACK */
@@ -2571,7 +2541,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2651,14 +2621,6 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-extern int armv4_5_run_algorithm_inner(struct target *target,
-       int num_mem_params, struct mem_param *mem_params,
-       int num_reg_params, struct reg_param *reg_params,
-       uint32_t entry_point, uint32_t exit_point,
-       int timeout_ms, void *arch_info,
-       int (*run_it)(struct target *target, uint32_t exit_point,
-                       int timeout_ms, void *arch_info));
-
 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        int retval;
@@ -2693,12 +2655,12 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
                }
        }
 
-       struct armv4_5_algorithm armv4_5_info;
+       struct arm_algorithm armv4_5_info;
        struct reg_param reg_params[1];
 
-       armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
-       armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+       armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
+       armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 
@@ -2831,22 +2793,40 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 
        if (CMD_ARGC > 0)
        {
-               COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting_active);
+               int semihosting;
+
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+               if (!target_was_examined(target))
+               {
+                       LOG_ERROR("Target not examined yet");
+                       return ERROR_FAIL;
+               }
 
-               /* TODO: support other methods if vector catch is unavailable */
                if (arm7_9->has_vector_catch) {
-                       struct reg *vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
+                       struct reg *vector_catch = &arm7_9->eice_cache
+                                       ->reg_list[EICE_VEC_CATCH];
+
                        if (!vector_catch->valid)
                                embeddedice_read_reg(vector_catch);
-                       buf_set_u32(vector_catch->value, 2, 1, semihosting_active);
+                       buf_set_u32(vector_catch->value, 2, 1, semihosting);
                        embeddedice_store_reg(vector_catch);
-               } else if (semihosting_active) {
-                       command_print(CMD_CTX, "vector catch unavailable");
-                       semihosting_active = 0;
+               } else {
+                       /* TODO: allow optional high vectors and/or BKPT_HARD */
+                       if (semihosting)
+                               breakpoint_add(target, 8, 4, BKPT_SOFT);
+                       else
+                               breakpoint_remove(target, 8); 
                }
+
+               /* FIXME never let that "catch" be dropped! */
+               arm7_9->armv4_5_common.is_semihosting = semihosting;
+
        }
 
-       command_print(CMD_CTX, "semihosting is %s", (semihosting_active) ? "enabled" : "disabled");
+       command_print(CMD_CTX, "semihosting is %s",
+                       arm7_9->armv4_5_common.is_semihosting
+                       ? "enabled" : "disabled");
 
        return ERROR_OK;
 }
@@ -2873,7 +2853,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
-       if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+       retval = arm_init_arch_info(target, armv4_5);
+       if (retval != ERROR_OK)
                return retval;
 
        return target_register_timer_callback(arm7_9_handle_target_request,
@@ -2883,32 +2864,32 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 static const struct command_registration arm7_9_any_command_handlers[] = {
        {
                "dbgrq",
-               .handler = &handle_arm7_9_dbgrq_command,
+               .handler = handle_arm7_9_dbgrq_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable|disable>",
+               .usage = "['enable'|'disable']",
                .help = "use EmbeddedICE dbgrq instead of breakpoint "
                        "for target halt requests",
        },
        {
                "fast_memory_access",
-               .handler = &handle_arm7_9_fast_memory_access_command,
+               .handler = handle_arm7_9_fast_memory_access_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable|disable>",
+               .usage = "['enable'|'disable']",
                .help = "use fast memory accesses instead of slower "
                        "but potentially safer accesses",
        },
        {
                "dcc_downloads",
-               .handler = &handle_arm7_9_dcc_downloads_command,
+               .handler = handle_arm7_9_dcc_downloads_command,
                .mode = COMMAND_ANY,
-               .usage = "<enable | disable>",
+               .usage = "['enable'|'disable']",
                .help = "use DCC downloads for larger memory writes",
        },
        {
                "semihosting",
-               .handler = &handle_arm7_9_semihosting_command,
+               .handler = handle_arm7_9_semihosting_command,
                .mode = COMMAND_EXEC,
-               .usage = "<enable | disable>",
+               .usage = "['enable'|'disable']",
                .help = "activate support for semihosting operations",
        },
        COMMAND_REGISTRATION_DONE
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