-/***************************************************************************\r
- * Copyright (C) 2005 by Dominic Rath *\r
- * Dominic.Rath@gmx.de *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "arm720t.h"\r
-#include "jtag.h"\r
-#include "log.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-#if 0\r
-#define _DEBUG_INSTRUCTION_EXECUTION_\r
-#endif\r
-\r
-/* cli handling */\r
-int arm720t_register_commands(struct command_context_s *cmd_ctx);\r
-\r
-int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-\r
-/* forward declarations */\r
-int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);\r
-int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);\r
-int arm720t_quit();\r
-int arm720t_arch_state(struct target_s *target);\r
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
-int arm720t_soft_reset_halt(struct target_s *target);\r
-\r
-target_type_t arm720t_target =\r
-{\r
- .name = "arm720t",\r
-\r
- .poll = arm7_9_poll,\r
- .arch_state = arm720t_arch_state,\r
-\r
- .halt = arm7_9_halt,\r
- .resume = arm7_9_resume,\r
- .step = arm7_9_step,\r
-\r
- .assert_reset = arm7_9_assert_reset,\r
- .deassert_reset = arm7_9_deassert_reset,\r
- .soft_reset_halt = arm720t_soft_reset_halt,\r
- .prepare_reset_halt = arm7_9_prepare_reset_halt,\r
- \r
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,\r
-\r
- .read_memory = arm720t_read_memory,\r
- .write_memory = arm720t_write_memory,\r
- .bulk_write_memory = arm7_9_bulk_write_memory,\r
- .checksum_memory = arm7_9_checksum_memory,\r
- \r
- .run_algorithm = armv4_5_run_algorithm,\r
-\r
- .add_breakpoint = arm7_9_add_breakpoint,\r
- .remove_breakpoint = arm7_9_remove_breakpoint,\r
- .add_watchpoint = arm7_9_add_watchpoint,\r
- .remove_watchpoint = arm7_9_remove_watchpoint,\r
-\r
- .register_commands = arm720t_register_commands,\r
- .target_command = arm720t_target_command,\r
- .init_target = arm720t_init_target,\r
- .quit = arm720t_quit\r
-};\r
-\r
-int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
- scan_field_t fields[2];\r
- u8 out_buf[4];\r
- u8 instruction_buf = instruction;\r
- \r
- buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));\r
- \r
- jtag_add_end_state(TAP_PD);\r
- arm_jtag_scann(jtag_info, 0xf);\r
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
- \r
- fields[0].device = jtag_info->chain_pos;\r
- fields[0].num_bits = 1;\r
- fields[0].out_value = &instruction_buf;\r
- fields[0].out_mask = NULL;\r
- fields[0].in_value = NULL;\r
- fields[0].in_check_value = NULL;\r
- fields[0].in_check_mask = NULL;\r
- fields[0].in_handler = NULL;\r
- fields[0].in_handler_priv = NULL;\r
-\r
- fields[1].device = jtag_info->chain_pos;\r
- fields[1].num_bits = 32;\r
- fields[1].out_value = out_buf;\r
- fields[1].out_mask = NULL;\r
- fields[1].in_value = NULL;\r
- if (in)\r
- {\r
- fields[1].in_handler = arm_jtag_buf_to_u32_flip;\r
- fields[1].in_handler_priv = in;\r
- } else\r
- {\r
- fields[1].in_handler = NULL;\r
- fields[1].in_handler_priv = NULL;\r
- }\r
- fields[1].in_check_value = NULL;\r
- fields[1].in_check_mask = NULL;\r
- \r
- jtag_add_dr_scan(2, fields, -1);\r
-\r
- if (clock)\r
- jtag_add_runtest(0, -1);\r
-\r
-#ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
- jtag_execute_queue();\r
-\r
- if (in)\r
- DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);\r
- else\r
- DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);\r
-#else\r
- DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)\r
-{\r
- /* fetch CP15 opcode */\r
- arm720t_scan_cp15(target, opcode, NULL, 1, 1);\r
- /* "DECODE" stage */\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
- /* "EXECUTE" stage (1) */\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);\r
- arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
- /* "EXECUTE" stage (2) */\r
- arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
- /* "EXECUTE" stage (3), CDATA is read */\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)\r
-{\r
- /* fetch CP15 opcode */\r
- arm720t_scan_cp15(target, opcode, NULL, 1, 1);\r
- /* "DECODE" stage */\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
- /* "EXECUTE" stage (1) */\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);\r
- arm720t_scan_cp15(target, 0x0, NULL, 0, 1);\r
- /* "EXECUTE" stage (2) */\r
- arm720t_scan_cp15(target, value, NULL, 0, 1);\r
- arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-u32 arm720t_get_ttb(target_t *target)\r
-{\r
- u32 ttb = 0x0;\r
-\r
- arm720t_read_cp15(target, 0xee120f10, &ttb);\r
- jtag_execute_queue();\r
- \r
- ttb &= 0xffffc000;\r
- \r
- return ttb;\r
-}\r
-\r
-void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
-{\r
- u32 cp15_control;\r
-\r
- /* read cp15 control register */\r
- arm720t_read_cp15(target, 0xee110f10, &cp15_control);\r
- jtag_execute_queue();\r
- \r
- if (mmu)\r
- cp15_control &= ~0x1U;\r
- \r
- if (d_u_cache || i_cache)\r
- cp15_control &= ~0x4U;\r
-\r
- arm720t_write_cp15(target, 0xee010f10, cp15_control);\r
-}\r
-\r
-void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
-{\r
- u32 cp15_control;\r
-\r
- /* read cp15 control register */\r
- arm720t_read_cp15(target, 0xee110f10, &cp15_control);\r
- jtag_execute_queue();\r
- \r
- if (mmu)\r
- cp15_control |= 0x1U;\r
- \r
- if (d_u_cache || i_cache)\r
- cp15_control |= 0x4U;\r
- \r
- arm720t_write_cp15(target, 0xee010f10, cp15_control);\r
-}\r
-\r
-void arm720t_post_debug_entry(target_t *target)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
- arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
- \r
- /* examine cp15 control reg */\r
- arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);\r
- jtag_execute_queue();\r
- DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);\r
-\r
- arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;\r
- arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;\r
- arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;\r
-\r
- /* save i/d fault status and address register */\r
- arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);\r
- arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);\r
- jtag_execute_queue();\r
-}\r
-\r
-void arm720t_pre_restore_context(target_t *target)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
- arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
- \r
- /* restore i/d fault status and address register */\r
- arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);\r
- arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);\r
-}\r
-\r
-int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9;\r
- arm7tdmi_common_t *arm7tdmi;\r
- arm720t_common_t *arm720t;\r
- \r
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
- {\r
- return -1;\r
- }\r
- \r
- arm7_9 = armv4_5->arch_info;\r
- if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)\r
- {\r
- return -1;\r
- }\r
- \r
- arm7tdmi = arm7_9->arch_info;\r
- if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)\r
- {\r
- return -1;\r
- }\r
- \r
- arm720t = arm7tdmi->arch_info;\r
- if (arm720t->common_magic != ARM720T_COMMON_MAGIC)\r
- {\r
- return -1;\r
- }\r
- \r
- *armv4_5_p = armv4_5;\r
- *arm7_9_p = arm7_9;\r
- *arm7tdmi_p = arm7tdmi;\r
- *arm720t_p = arm720t;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_arch_state(struct target_s *target)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
- arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
- \r
- char *state[] = \r
- {\r
- "disabled", "enabled"\r
- };\r
- \r
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
- {\r
- ERROR("BUG: called for a non-ARMv4/5 target");\r
- exit(-1);\r
- }\r
- \r
- USER("target halted in %s state due to %s, current mode: %s\n"\r
- "cpsr: 0x%8.8x pc: 0x%8.8x\n"\r
- "MMU: %s, Cache: %s",\r
- armv4_5_state_strings[armv4_5->core_state],\r
- target_debug_reason_strings[target->debug_reason],\r
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],\r
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),\r
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),\r
- state[arm720t->armv4_5_mmu.mmu_enabled],\r
- state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
-{\r
- int retval;\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
- arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
- \r
- /* disable cache, but leave MMU enabled */\r
- if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)\r
- arm720t_disable_mmu_caches(target, 0, 1, 0);\r
- \r
- retval = arm7_9_read_memory(target, address, size, count, buffer);\r
- \r
- if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)\r
- arm720t_enable_mmu_caches(target, 0, 1, 0);\r
- \r
- return retval;\r
-}\r
-\r
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
-{\r
- int retval;\r
- \r
- if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)\r
- return retval;\r
-\r
- return retval;\r
-}\r
-\r
-int arm720t_soft_reset_halt(struct target_s *target)\r
-{\r
- armv4_5_common_t *armv4_5 = target->arch_info;\r
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
- arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;\r
- arm720t_common_t *arm720t = arm7tdmi->arch_info;\r
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];\r
- \r
- if (target->state == TARGET_RUNNING)\r
- {\r
- target->type->halt(target);\r
- }\r
- \r
- while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)\r
- {\r
- embeddedice_read_reg(dbg_stat);\r
- jtag_execute_queue();\r
- }\r
- \r
- target->state = TARGET_HALTED;\r
- \r
- /* SVC, ARM state, IRQ and FIQ disabled */\r
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);\r
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;\r
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;\r
- \r
- /* start fetching from 0x0 */\r
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);\r
- armv4_5->core_cache->reg_list[15].dirty = 1;\r
- armv4_5->core_cache->reg_list[15].valid = 1;\r
- \r
- armv4_5->core_mode = ARMV4_5_MODE_SVC;\r
- armv4_5->core_state = ARMV4_5_STATE_ARM;\r
- \r
- arm720t_disable_mmu_caches(target, 1, 1, 1);\r
- arm720t->armv4_5_mmu.mmu_enabled = 0;\r
- arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;\r
- arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;\r
-\r
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)\r
-{\r
- arm7tdmi_init_target(cmd_ctx, target);\r
- \r
- return ERROR_OK;\r
- \r
-}\r
-\r
-int arm720t_quit()\r
-{\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)\r
-{\r
- arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;\r
- arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;\r
- \r
- arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);\r
-\r
- arm7tdmi->arch_info = arm720t;\r
- arm720t->common_magic = ARM720T_COMMON_MAGIC;\r
- \r
- arm7_9->post_debug_entry = arm720t_post_debug_entry;\r
- arm7_9->pre_restore_context = arm720t_pre_restore_context;\r
- \r
- arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;\r
- arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;\r
- arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;\r
- arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;\r
- arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;\r
- arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;\r
- arm720t->armv4_5_mmu.has_tiny_pages = 0;\r
- arm720t->armv4_5_mmu.mmu_enabled = 0;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)\r
-{\r
- int chain_pos;\r
- char *variant = NULL;\r
- arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));\r
- \r
- if (argc < 4)\r
- {\r
- ERROR("'target arm720t' requires at least one additional argument");\r
- exit(-1);\r
- }\r
- \r
- chain_pos = strtoul(args[3], NULL, 0);\r
- \r
- if (argc >= 5)\r
- variant = args[4];\r
- \r
- DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);\r
- \r
- arm720t_init_arch_info(target, arm720t, chain_pos, variant);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- int retval;\r
- command_t *arm720t_cmd;\r
- \r
- \r
- retval = arm7tdmi_register_commands(cmd_ctx);\r
- \r
- arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");\r
-\r
- register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");\r
- register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");\r
-\r
- register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");\r
- register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");\r
- register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");\r
-\r
- register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");\r
- register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");\r
- register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- int retval;\r
- target_t *target = get_current_target(cmd_ctx);\r
- armv4_5_common_t *armv4_5;\r
- arm7_9_common_t *arm7_9;\r
- arm7tdmi_common_t *arm7tdmi;\r
- arm720t_common_t *arm720t;\r
- arm_jtag_t *jtag_info;\r
-\r
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "current target isn't an ARM720t target");\r
- return ERROR_OK;\r
- }\r
- \r
- jtag_info = &arm7_9->jtag_info;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
- return ERROR_OK;\r
- }\r
-\r
- /* one or more argument, access a single register (write if second argument is given */\r
- if (argc >= 1)\r
- {\r
- u32 opcode = strtoul(args[0], NULL, 0);\r
-\r
- if (argc == 1)\r
- {\r
- u32 value;\r
- if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);\r
- return ERROR_OK;\r
- }\r
- jtag_execute_queue();\r
- \r
- command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);\r
- }\r
- else if (argc == 2)\r
- {\r
- u32 value = strtoul(args[1], NULL, 0);\r
- if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);\r
- return ERROR_OK;\r
- }\r
- command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);\r
- }\r
- }\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
-{ \r
- target_t *target = get_current_target(cmd_ctx);\r
- armv4_5_common_t *armv4_5;\r
- arm7_9_common_t *arm7_9;\r
- arm7tdmi_common_t *arm7tdmi;\r
- arm720t_common_t *arm720t;\r
- arm_jtag_t *jtag_info;\r
-\r
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "current target isn't an ARM720t target");\r
- return ERROR_OK;\r
- }\r
- \r
- jtag_info = &arm7_9->jtag_info;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
- return ERROR_OK;\r
- }\r
- \r
- return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
-}\r
-\r
-int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
-{ \r
- target_t *target = get_current_target(cmd_ctx);\r
- armv4_5_common_t *armv4_5;\r
- arm7_9_common_t *arm7_9;\r
- arm7tdmi_common_t *arm7tdmi;\r
- arm720t_common_t *arm720t;\r
- arm_jtag_t *jtag_info;\r
-\r
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "current target isn't an ARM720t target");\r
- return ERROR_OK;\r
- }\r
- \r
- jtag_info = &arm7_9->jtag_info;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
- return ERROR_OK;\r
- }\r
- \r
- return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
-}\r
-\r
-int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
-{ \r
- target_t *target = get_current_target(cmd_ctx);\r
- armv4_5_common_t *armv4_5;\r
- arm7_9_common_t *arm7_9;\r
- arm7tdmi_common_t *arm7tdmi;\r
- arm720t_common_t *arm720t;\r
- arm_jtag_t *jtag_info;\r
-\r
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "current target isn't an ARM720t target");\r
- return ERROR_OK;\r
- }\r
- \r
- jtag_info = &arm7_9->jtag_info;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
- return ERROR_OK;\r
- }\r
- \r
- return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);\r
-}\r
-\r
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2009 by Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "arm720t.h"
+#include "time_support.h"
+#include "target_type.h"
+
+
+/*
+ * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
+ * ARM DDI 0229C especially Chapter 9 about debug support.
+ */
+
+#if 0
+#define _DEBUG_INSTRUCTION_EXECUTION_
+#endif
+
+static int arm720t_scan_cp15(target_t *target,
+ uint32_t out, uint32_t *in, int instruction, int clock)
+{
+ int retval;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+ arm_jtag_t *jtag_info;
+ scan_field_t fields[2];
+ uint8_t out_buf[4];
+ uint8_t instruction_buf = instruction;
+
+ jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
+
+ buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
+
+ jtag_set_end_state(TAP_DRPAUSE);
+ if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 1;
+ fields[0].out_value = &instruction_buf;
+ fields[0].in_value = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 32;
+ fields[1].out_value = out_buf;
+ fields[1].in_value = NULL;
+
+ if (in)
+ {
+ fields[1].in_value = (uint8_t *)in;
+ jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
+ } else
+ {
+ jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ }
+
+ if (clock)
+ jtag_add_runtest(0, jtag_get_end_state());
+
+#ifdef _DEBUG_INSTRUCTION_EXECUTION_
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (in)
+ LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
+ else
+ LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+#else
+ LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
+#endif
+
+ return ERROR_OK;
+}
+
+static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
+{
+ /* fetch CP15 opcode */
+ arm720t_scan_cp15(target, opcode, NULL, 1, 1);
+ /* "DECODE" stage */
+ arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
+ /* "EXECUTE" stage (1) */
+ arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
+ arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
+ /* "EXECUTE" stage (2) */
+ arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
+ /* "EXECUTE" stage (3), CDATA is read */
+ arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
+
+ return ERROR_OK;
+}
+
+static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
+{
+ /* fetch CP15 opcode */
+ arm720t_scan_cp15(target, opcode, NULL, 1, 1);
+ /* "DECODE" stage */
+ arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
+ /* "EXECUTE" stage (1) */
+ arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
+ arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
+ /* "EXECUTE" stage (2) */
+ arm720t_scan_cp15(target, value, NULL, 0, 1);
+ arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
+
+ return ERROR_OK;
+}
+
+static uint32_t arm720t_get_ttb(target_t *target)
+{
+ uint32_t ttb = 0x0;
+
+ arm720t_read_cp15(target, 0xee120f10, &ttb);
+ jtag_execute_queue();
+
+ ttb &= 0xffffc000;
+
+ return ttb;
+}
+
+static void arm720t_disable_mmu_caches(target_t *target,
+ int mmu, int d_u_cache, int i_cache)
+{
+ uint32_t cp15_control;
+
+ /* read cp15 control register */
+ arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+ jtag_execute_queue();
+
+ if (mmu)
+ cp15_control &= ~0x1U;
+
+ if (d_u_cache || i_cache)
+ cp15_control &= ~0x4U;
+
+ arm720t_write_cp15(target, 0xee010f10, cp15_control);
+}
+
+static void arm720t_enable_mmu_caches(target_t *target,
+ int mmu, int d_u_cache, int i_cache)
+{
+ uint32_t cp15_control;
+
+ /* read cp15 control register */
+ arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+ jtag_execute_queue();
+
+ if (mmu)
+ cp15_control |= 0x1U;
+
+ if (d_u_cache || i_cache)
+ cp15_control |= 0x4U;
+
+ arm720t_write_cp15(target, 0xee010f10, cp15_control);
+}
+
+static void arm720t_post_debug_entry(target_t *target)
+{
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+
+ /* examine cp15 control reg */
+ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+ jtag_execute_queue();
+ LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
+
+ arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
+ arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
+ arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+
+ /* save i/d fault status and address register */
+ arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+ arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+ jtag_execute_queue();
+}
+
+static void arm720t_pre_restore_context(target_t *target)
+{
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+
+ /* restore i/d fault status and address register */
+ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
+ arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
+}
+
+static int arm720t_verify_pointer(struct command_context_s *cmd_ctx,
+ struct arm720t_common_s *arm720t)
+{
+ if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
+ command_print(cmd_ctx, "target is not an ARM720");
+ return ERROR_TARGET_INVALID;
+ }
+ return ERROR_OK;
+}
+
+static int arm720t_arch_state(struct target_s *target)
+{
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+ struct armv4_5_common_s *armv4_5;
+
+ static const char *state[] =
+ {
+ "disabled", "enabled"
+ };
+
+ armv4_5 = &arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common;
+
+ LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
+ "MMU: %s, Cache: %s",
+ armv4_5_state_strings[armv4_5->core_state],
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
+ armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+ state[arm720t->armv4_5_mmu.mmu_enabled],
+ state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
+
+ return ERROR_OK;
+}
+
+static int arm720_mmu(struct target_s *target, int *enabled)
+{
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("%s: target not halted", __func__);
+ return ERROR_TARGET_INVALID;
+ }
+
+ *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
+ return ERROR_OK;
+}
+
+static int arm720_virt2phys(struct target_s *target,
+ uint32_t virt, uint32_t *phys)
+{
+ /** @todo Implement this! */
+ LOG_ERROR("%s: not implemented", __func__);
+ return ERROR_FAIL;
+}
+
+static int arm720t_read_memory(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ int retval;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+
+ /* disable cache, but leave MMU enabled */
+ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ arm720t_disable_mmu_caches(target, 0, 1, 0);
+
+ retval = arm7_9_read_memory(target, address, size, count, buffer);
+
+ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ arm720t_enable_mmu_caches(target, 0, 1, 0);
+
+ return retval;
+}
+
+static int arm720t_read_phys_memory(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+
+ return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+static int arm720t_write_phys_memory(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+
+ return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+static int arm720t_soft_reset_halt(struct target_s *target)
+{
+ int retval = ERROR_OK;
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+ reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
+ .eice_cache->reg_list[EICE_DBG_STAT];
+ struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
+ .arm7_9_common.armv4_5_common;
+
+ if ((retval = target_halt(target)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ long long then = timeval_ms();
+ int timeout;
+ while (!(timeout = ((timeval_ms()-then) > 1000)))
+ {
+ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+ {
+ embeddedice_read_reg(dbg_stat);
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+ } else
+ {
+ break;
+ }
+ if (debug_level >= 3)
+ {
+ alive_sleep(100);
+ } else
+ {
+ keep_alive();
+ }
+ }
+ if (timeout)
+ {
+ LOG_ERROR("Failed to halt CPU after 1 sec");
+ return ERROR_TARGET_TIMEOUT;
+ }
+
+ target->state = TARGET_HALTED;
+
+ /* SVC, ARM state, IRQ and FIQ disabled */
+ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
+ armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+ armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+
+ /* start fetching from 0x0 */
+ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
+ armv4_5->core_cache->reg_list[15].dirty = 1;
+ armv4_5->core_cache->reg_list[15].valid = 1;
+
+ armv4_5->core_mode = ARMV4_5_MODE_SVC;
+ armv4_5->core_state = ARMV4_5_STATE_ARM;
+
+ arm720t_disable_mmu_caches(target, 1, 1, 1);
+ arm720t->armv4_5_mmu.mmu_enabled = 0;
+ arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
+ arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+
+ if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
+static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+{
+ return arm7tdmi_init_target(cmd_ctx, target);
+}
+
+static int arm720t_init_arch_info(target_t *target,
+ arm720t_common_t *arm720t, struct jtag_tap *tap)
+{
+ arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
+ arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
+
+ arm7tdmi_init_arch_info(target, arm7tdmi, tap);
+
+ arm720t->common_magic = ARM720T_COMMON_MAGIC;
+
+ arm7_9->post_debug_entry = arm720t_post_debug_entry;
+ arm7_9->pre_restore_context = arm720t_pre_restore_context;
+
+ arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
+ arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
+ arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
+ arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
+ arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
+ arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
+ arm720t->armv4_5_mmu.has_tiny_pages = 0;
+ arm720t->armv4_5_mmu.mmu_enabled = 0;
+
+ return ERROR_OK;
+}
+
+static int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ struct arm720t_common_s *arm720t = calloc(1, sizeof(*arm720t));
+
+ arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common.is_armv4 = true;
+ return arm720t_init_arch_info(target, arm720t, target->tap);
+}
+
+COMMAND_HANDLER(arm720t_handle_cp15_command)
+{
+ int retval;
+ target_t *target = get_current_target(cmd_ctx);
+ struct arm720t_common_s *arm720t = target_to_arm720(target);
+ arm_jtag_t *jtag_info;
+
+ retval = arm720t_verify_pointer(cmd_ctx, arm720t);
+ if (retval != ERROR_OK)
+ return retval;
+
+ jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_OK;
+ }
+
+ /* one or more argument, access a single register (write if second argument is given */
+ if (argc >= 1)
+ {
+ uint32_t opcode;
+ COMMAND_PARSE_NUMBER(u32, args[0], opcode);
+
+ if (argc == 1)
+ {
+ uint32_t value;
+ if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
+ return ERROR_OK;
+ }
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
+ }
+ else if (argc == 2)
+ {
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, args[1], value);
+
+ if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
+ return ERROR_OK;
+ }
+ command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
+ }
+ }
+
+ return ERROR_OK;
+}
+
+static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+
+ return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
+
+}
+
+static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+
+ return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
+}
+
+static int arm720t_register_commands(struct command_context_s *cmd_ctx)
+{
+ int retval;
+ command_t *arm720t_cmd;
+
+
+ retval = arm7_9_register_commands(cmd_ctx);
+
+ arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t",
+ NULL, COMMAND_ANY,
+ "arm720t specific commands");
+
+ register_command(cmd_ctx, arm720t_cmd, "cp15",
+ arm720t_handle_cp15_command, COMMAND_EXEC,
+ "display/modify cp15 register <opcode> [value]");
+
+ return ERROR_OK;
+}
+
+/** Holds methods for ARM720 targets. */
+target_type_t arm720t_target =
+{
+ .name = "arm720t",
+
+ .poll = arm7_9_poll,
+ .arch_state = arm720t_arch_state,
+
+ .halt = arm7_9_halt,
+ .resume = arm7_9_resume,
+ .step = arm7_9_step,
+
+ .assert_reset = arm7_9_assert_reset,
+ .deassert_reset = arm7_9_deassert_reset,
+ .soft_reset_halt = arm720t_soft_reset_halt,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = arm720t_read_memory,
+ .write_memory = arm7_9_write_memory,
+ .read_phys_memory = arm720t_read_phys_memory,
+ .write_phys_memory = arm720t_write_phys_memory,
+ .mmu = arm720_mmu,
+ .virt2phys = arm720_virt2phys,
+
+ .bulk_write_memory = arm7_9_bulk_write_memory,
+ .checksum_memory = arm7_9_checksum_memory,
+ .blank_check_memory = arm7_9_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = arm7_9_add_breakpoint,
+ .remove_breakpoint = arm7_9_remove_breakpoint,
+ .add_watchpoint = arm7_9_add_watchpoint,
+ .remove_watchpoint = arm7_9_remove_watchpoint,
+
+ .register_commands = arm720t_register_commands,
+ .target_create = arm720t_target_create,
+ .init_target = arm720t_init_target,
+ .examine = arm7tdmi_examine,
+ .mrc = arm720t_mrc,
+ .mcr = arm720t_mcr,
+
+};
Code Review / openocd.git / blobdiff