-/***************************************************************************\r
- * Copyright (C) 2005 by Dominic Rath *\r
- * Dominic.Rath@gmx.de *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "replacements.h"\r
-\r
-#include "str9x.h"\r
-#include "flash.h"\r
-#include "target.h"\r
-#include "log.h"\r
-#include "armv4_5.h"\r
-#include "arm966e.h"\r
-#include "algorithm.h"\r
-#include "binarybuffer.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-#include <unistd.h>\r
-\r
-str9x_mem_layout_t mem_layout_str9bank0[] = {\r
- {0x00000000, 0x10000, 0x01},\r
- {0x00010000, 0x10000, 0x02},\r
- {0x00020000, 0x10000, 0x04},\r
- {0x00030000, 0x10000, 0x08},\r
- {0x00040000, 0x10000, 0x10},\r
- {0x00050000, 0x10000, 0x20},\r
- {0x00060000, 0x10000, 0x40},\r
- {0x00070000, 0x10000, 0x80},\r
-};\r
-\r
-str9x_mem_layout_t mem_layout_str9bank1[] = {\r
- {0x00000000, 0x02000, 0x100},\r
- {0x00002000, 0x02000, 0x200},\r
- {0x00004000, 0x02000, 0x400},\r
- {0x00006000, 0x02000, 0x800}\r
-};\r
-\r
-static u32 bank1start = 0x00080000;\r
-\r
-int str9x_register_commands(struct command_context_s *cmd_ctx);\r
-int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
-int str9x_erase(struct flash_bank_s *bank, int first, int last);\r
-int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);\r
-int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
-int str9x_probe(struct flash_bank_s *bank);\r
-int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int str9x_protect_check(struct flash_bank_s *bank);\r
-int str9x_erase_check(struct flash_bank_s *bank);\r
-int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
-\r
-int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-\r
-flash_driver_t str9x_flash =\r
-{\r
- .name = "str9x",\r
- .register_commands = str9x_register_commands,\r
- .flash_bank_command = str9x_flash_bank_command,\r
- .erase = str9x_erase,\r
- .protect = str9x_protect,\r
- .write = str9x_write,\r
- .probe = str9x_probe,\r
- .auto_probe = str9x_probe,\r
- .erase_check = str9x_erase_check,\r
- .protect_check = str9x_protect_check,\r
- .info = str9x_info\r
-};\r
-\r
-int str9x_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);\r
- \r
- register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,\r
- "configure str9 flash controller");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_build_block_list(struct flash_bank_s *bank)\r
-{\r
- str9x_flash_bank_t *str9x_info = bank->driver_priv;\r
- \r
- int i;\r
- int num_sectors = 0;\r
- int b0_sectors = 0, b1_sectors = 0;\r
- \r
- switch (bank->size)\r
- {\r
- case (256 * 1024):\r
- b0_sectors = 4;\r
- break;\r
- case (512 * 1024):\r
- b0_sectors = 8;\r
- break;\r
- case (32 * 1024):\r
- b1_sectors = 4;\r
- bank1start = bank->base;\r
- break;\r
- default:\r
- ERROR("BUG: unknown bank->size encountered");\r
- exit(-1);\r
- }\r
- \r
- num_sectors = b0_sectors + b1_sectors;\r
- \r
- bank->num_sectors = num_sectors;\r
- bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);\r
- str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);\r
- \r
- num_sectors = 0;\r
- \r
- for (i = 0; i < b0_sectors; i++)\r
- {\r
- bank->sectors[num_sectors].offset = mem_layout_str9bank0[i].sector_start;\r
- bank->sectors[num_sectors].size = mem_layout_str9bank0[i].sector_size;\r
- bank->sectors[num_sectors].is_erased = -1;\r
- bank->sectors[num_sectors].is_protected = 1;\r
- str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank0[i].sector_bit;\r
- }\r
-\r
- for (i = 0; i < b1_sectors; i++)\r
- {\r
- bank->sectors[num_sectors].offset = mem_layout_str9bank1[i].sector_start;\r
- bank->sectors[num_sectors].size = mem_layout_str9bank1[i].sector_size;\r
- bank->sectors[num_sectors].is_erased = -1;\r
- bank->sectors[num_sectors].is_protected = 1;\r
- str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank1[i].sector_bit;\r
- }\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-/* flash bank str9x <base> <size> 0 0 <target#>\r
- */\r
-int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
-{\r
- str9x_flash_bank_t *str9x_info;\r
- \r
- if (argc < 6)\r
- {\r
- WARNING("incomplete flash_bank str9x configuration");\r
- return ERROR_FLASH_BANK_INVALID;\r
- }\r
- \r
- str9x_info = malloc(sizeof(str9x_flash_bank_t));\r
- bank->driver_priv = str9x_info;\r
- \r
- str9x_build_block_list(bank);\r
- \r
- str9x_info->write_algorithm = NULL;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_blank_check(struct flash_bank_s *bank, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- u8 *buffer;\r
- int i;\r
- int nBytes;\r
- \r
- if ((first < 0) || (last > bank->num_sectors))\r
- return ERROR_FLASH_SECTOR_INVALID;\r
-\r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- buffer = malloc(256);\r
- \r
- for (i = first; i <= last; i++)\r
- {\r
- bank->sectors[i].is_erased = 1;\r
-\r
- target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);\r
- \r
- for (nBytes = 0; nBytes < 256; nBytes++)\r
- {\r
- if (buffer[nBytes] != 0xFF)\r
- {\r
- bank->sectors[i].is_erased = 0;\r
- break;\r
- }\r
- } \r
- }\r
- \r
- free(buffer);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_protect_check(struct flash_bank_s *bank)\r
-{\r
- str9x_flash_bank_t *str9x_info = bank->driver_priv;\r
- target_t *target = bank->target;\r
- \r
- int i;\r
- u32 adr;\r
- u16 status;\r
-\r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- /* read level one protection */\r
- \r
- adr = bank1start + 0x10;\r
- \r
- target_write_u16(target, adr, 0x90);\r
- target_read_u16(target, adr, &status);\r
- target_write_u16(target, adr, 0xFF);\r
- \r
- for (i = 0; i < bank->num_sectors; i++)\r
- {\r
- if (status & str9x_info->sector_bits[i])\r
- bank->sectors[i].is_protected = 1;\r
- else\r
- bank->sectors[i].is_protected = 0;\r
- }\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_erase(struct flash_bank_s *bank, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- int i;\r
- u32 adr;\r
- u8 status;\r
- \r
- for (i = first; i <= last; i++)\r
- {\r
- adr = bank->base + bank->sectors[i].offset;\r
- \r
- /* erase sectors */\r
- target_write_u16(target, adr, 0x20);\r
- target_write_u16(target, adr, 0xD0);\r
- \r
- /* get status */\r
- target_write_u16(target, adr, 0x70);\r
- \r
- while (1) {\r
- target_read_u8(target, adr, &status);\r
- if( status & 0x80 )\r
- break;\r
- usleep(1000);\r
- }\r
- \r
- /* clear status, also clear read array */\r
- target_write_u16(target, adr, 0x50);\r
- \r
- /* read array command */\r
- target_write_u16(target, adr, 0xFF);\r
- \r
- if( status & 0x22 )\r
- {\r
- ERROR("error erasing flash bank, status: 0x%x", status);\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- }\r
- \r
- for (i = first; i <= last; i++)\r
- bank->sectors[i].is_erased = 1;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- int i;\r
- u32 adr;\r
- u8 status;\r
- \r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- for (i = first; i <= last; i++)\r
- {\r
- /* Level One Protection */\r
- \r
- adr = bank->base + bank->sectors[i].offset;\r
- \r
- target_write_u16(target, adr, 0x60);\r
- if( set )\r
- target_write_u16(target, adr, 0x01);\r
- else\r
- target_write_u16(target, adr, 0xD0);\r
- \r
- /* query status */\r
- target_read_u8(target, adr, &status);\r
- }\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- str9x_flash_bank_t *str9x_info = bank->driver_priv;\r
- target_t *target = bank->target;\r
- u32 buffer_size = 8192;\r
- working_area_t *source;\r
- u32 address = bank->base + offset;\r
- reg_param_t reg_params[4];\r
- armv4_5_algorithm_t armv4_5_info;\r
- int retval;\r
- \r
- u32 str9x_flash_write_code[] = {\r
- /* write: */\r
- 0xe3c14003, /* bic r4, r1, #3 */\r
- 0xe3a03040, /* mov r3, #0x40 */\r
- 0xe1c430b0, /* strh r3, [r4, #0] */\r
- 0xe0d030b2, /* ldrh r3, [r0], #2 */\r
- 0xe0c130b2, /* strh r3, [r1], #2 */\r
- 0xe3a03070, /* mov r3, #0x70 */\r
- 0xe1c430b0, /* strh r3, [r4, #0] */\r
- /* busy: */\r
- 0xe5d43000, /* ldrb r3, [r4, #0] */\r
- 0xe3130080, /* tst r3, #0x80 */\r
- 0x0afffffc, /* beq busy */\r
- 0xe3a05050, /* mov r5, #0x50 */\r
- 0xe1c450b0, /* strh r5, [r4, #0] */\r
- 0xe3a050ff, /* mov r5, #0xFF */\r
- 0xe1c450b0, /* strh r5, [r4, #0] */\r
- 0xe3130012, /* tst r3, #0x12 */\r
- 0x1a000001, /* bne exit */\r
- 0xe2522001, /* subs r2, r2, #1 */\r
- 0x1affffed, /* bne write */\r
- /* exit: */\r
- 0xeafffffe, /* b exit */\r
- };\r
- \r
- /* flash write code */\r
- if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)\r
- {\r
- WARNING("no working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- };\r
- \r
- target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);\r
-\r
- /* memory buffer */\r
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)\r
- {\r
- buffer_size /= 2;\r
- if (buffer_size <= 256)\r
- {\r
- /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */\r
- if (str9x_info->write_algorithm)\r
- target_free_working_area(target, str9x_info->write_algorithm);\r
- \r
- WARNING("no large enough working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- }\r
- }\r
- \r
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;\r
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;\r
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;\r
- \r
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT);\r
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);\r
- init_reg_param(®_params[2], "r2", 32, PARAM_OUT);\r
- init_reg_param(®_params[3], "r3", 32, PARAM_IN);\r
- \r
- while (count > 0)\r
- {\r
- u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;\r
- \r
- target_write_buffer(target, source->address, thisrun_count * 2, buffer);\r
- \r
- buf_set_u32(reg_params[0].value, 0, 32, source->address);\r
- buf_set_u32(reg_params[1].value, 0, 32, address);\r
- buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);\r
-\r
- if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)\r
- {\r
- target_free_working_area(target, source);\r
- target_free_working_area(target, str9x_info->write_algorithm);\r
- ERROR("error executing str9x flash write algorithm");\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- \r
- if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)\r
- {\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- \r
- buffer += thisrun_count * 2;\r
- address += thisrun_count * 2;\r
- count -= thisrun_count;\r
- }\r
- \r
- target_free_working_area(target, source);\r
- target_free_working_area(target, str9x_info->write_algorithm);\r
- \r
- destroy_reg_param(®_params[0]);\r
- destroy_reg_param(®_params[1]);\r
- destroy_reg_param(®_params[2]);\r
- destroy_reg_param(®_params[3]);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- target_t *target = bank->target;\r
- u32 words_remaining = (count / 2);\r
- u32 bytes_remaining = (count & 0x00000001);\r
- u32 address = bank->base + offset;\r
- u32 bytes_written = 0;\r
- u8 status;\r
- u32 retval;\r
- u32 check_address = offset;\r
- u32 bank_adr;\r
- int i;\r
- \r
- if (offset & 0x1)\r
- {\r
- WARNING("offset 0x%x breaks required 2-byte alignment", offset);\r
- return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
- }\r
- \r
- for (i = 0; i < bank->num_sectors; i++)\r
- {\r
- u32 sec_start = bank->sectors[i].offset;\r
- u32 sec_end = sec_start + bank->sectors[i].size;\r
- \r
- /* check if destination falls within the current sector */\r
- if ((check_address >= sec_start) && (check_address < sec_end))\r
- {\r
- /* check if destination ends in the current sector */\r
- if (offset + count < sec_end)\r
- check_address = offset + count;\r
- else\r
- check_address = sec_end;\r
- }\r
- }\r
- \r
- if (check_address != offset + count)\r
- return ERROR_FLASH_DST_OUT_OF_BANK;\r
- \r
- /* multiple half words (2-byte) to be programmed? */\r
- if (words_remaining > 0) \r
- {\r
- /* try using a block write */\r
- if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)\r
- {\r
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)\r
- {\r
- /* if block write failed (no sufficient working area),\r
- * we use normal (slow) single dword accesses */ \r
- WARNING("couldn't use block writes, falling back to single memory accesses");\r
- }\r
- else if (retval == ERROR_FLASH_OPERATION_FAILED)\r
- {\r
- ERROR("flash writing failed with error code: 0x%x", retval);\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- }\r
- else\r
- {\r
- buffer += words_remaining * 2;\r
- address += words_remaining * 2;\r
- words_remaining = 0;\r
- }\r
- }\r
-\r
- while (words_remaining > 0)\r
- {\r
- bank_adr = address & ~0x03;\r
- \r
- /* write data command */\r
- target_write_u16(target, bank_adr, 0x40);\r
- target->type->write_memory(target, address, 2, 1, buffer + bytes_written);\r
- \r
- /* get status command */\r
- target_write_u16(target, bank_adr, 0x70);\r
- \r
- while (1) {\r
- target_read_u8(target, bank_adr, &status);\r
- if( status & 0x80 )\r
- break;\r
- usleep(1000);\r
- }\r
- \r
- /* clear status reg and read array */\r
- target_write_u16(target, bank_adr, 0x50);\r
- target_write_u16(target, bank_adr, 0xFF);\r
- \r
- if (status & 0x10)\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- else if (status & 0x02)\r
- return ERROR_FLASH_OPERATION_FAILED;\r
-\r
- bytes_written += 2;\r
- words_remaining--;\r
- address += 2;\r
- }\r
- \r
- if (bytes_remaining)\r
- {\r
- u8 last_halfword[2] = {0xff, 0xff};\r
- int i = 0;\r
- \r
- while(bytes_remaining > 0)\r
- {\r
- last_halfword[i++] = *(buffer + bytes_written); \r
- bytes_remaining--;\r
- bytes_written++;\r
- }\r
- \r
- bank_adr = address & ~0x03;\r
- \r
- /* write data comamnd */\r
- target_write_u16(target, bank_adr, 0x40);\r
- target->type->write_memory(target, address, 2, 1, last_halfword);\r
- \r
- /* query status command */\r
- target_write_u16(target, bank_adr, 0x70);\r
- \r
- while (1) {\r
- target_read_u8(target, bank_adr, &status);\r
- if( status & 0x80 )\r
- break;\r
- usleep(1000);\r
- }\r
- \r
- /* clear status reg and read array */\r
- target_write_u16(target, bank_adr, 0x50);\r
- target_write_u16(target, bank_adr, 0xFF);\r
- \r
- if (status & 0x10)\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- else if (status & 0x02)\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_probe(struct flash_bank_s *bank)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_erase_check(struct flash_bank_s *bank)\r
-{\r
- return str9x_blank_check(bank, 0, bank->num_sectors - 1);\r
-}\r
-\r
-int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
-{\r
- snprintf(buf, buf_size, "str9x flash driver info" );\r
- return ERROR_OK;\r
-}\r
-\r
-int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- str9x_flash_bank_t *str9x_info;\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- \r
- if (argc < 5)\r
- {\r
- return ERROR_COMMAND_SYNTAX_ERROR;\r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- str9x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- /* config flash controller */\r
- target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));\r
- target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));\r
- target_write_u32(target, FLASH_BBADR, (strtoul(args[3], NULL, 0) >> 2));\r
- target_write_u32(target, FLASH_NBBADR, (strtoul(args[4], NULL, 0) >> 2));\r
-\r
- /* set bit 18 instruction TCM order as per flash programming manual */\r
- arm966e_write_cp15(target, 62, 0x40000);\r
- \r
- /* enable flash bank 1 */\r
- target_write_u32(target, FLASH_CR, 0x18);\r
- return ERROR_OK;\r
-}\r
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ *
+ * Copyright (C) 2008 by Oyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "str9x.h"
+#include "arm966e.h"
+#include "algorithm.h"
+
+
+static uint32_t bank1start = 0x00080000;
+
+static int str9x_build_block_list(struct flash_bank *bank)
+{
+ struct str9x_flash_bank *str9x_info = bank->driver_priv;
+
+ int i;
+ int num_sectors;
+ int b0_sectors = 0, b1_sectors = 0;
+ uint32_t offset = 0;
+
+ /* set if we have large flash str9 */
+ str9x_info->variant = 0;
+ str9x_info->bank1 = 0;
+
+ switch (bank->size)
+ {
+ case (256 * 1024):
+ b0_sectors = 4;
+ break;
+ case (512 * 1024):
+ b0_sectors = 8;
+ break;
+ case (1024 * 1024):
+ bank1start = 0x00100000;
+ str9x_info->variant = 1;
+ b0_sectors = 16;
+ break;
+ case (2048 * 1024):
+ bank1start = 0x00200000;
+ str9x_info->variant = 1;
+ b0_sectors = 32;
+ break;
+ case (128 * 1024):
+ str9x_info->variant = 1;
+ str9x_info->bank1 = 1;
+ b1_sectors = 8;
+ bank1start = bank->base;
+ break;
+ case (32 * 1024):
+ str9x_info->bank1 = 1;
+ b1_sectors = 4;
+ bank1start = bank->base;
+ break;
+ default:
+ LOG_ERROR("BUG: unknown bank->size encountered");
+ exit(-1);
+ }
+
+ num_sectors = b0_sectors + b1_sectors;
+
+ bank->num_sectors = num_sectors;
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
+ str9x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
+
+ num_sectors = 0;
+
+ for (i = 0; i < b0_sectors; i++)
+ {
+ bank->sectors[num_sectors].offset = offset;
+ bank->sectors[num_sectors].size = 0x10000;
+ offset += bank->sectors[i].size;
+ bank->sectors[num_sectors].is_erased = -1;
+ bank->sectors[num_sectors].is_protected = 1;
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
+ }
+
+ for (i = 0; i < b1_sectors; i++)
+ {
+ bank->sectors[num_sectors].offset = offset;
+ bank->sectors[num_sectors].size = str9x_info->variant == 0 ? 0x2000 : 0x4000;
+ offset += bank->sectors[i].size;
+ bank->sectors[num_sectors].is_erased = -1;
+ bank->sectors[num_sectors].is_protected = 1;
+ if (str9x_info->variant)
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
+ else
+ str9x_info->sector_bits[num_sectors++] = (1 << (i + 8));
+ }
+
+ return ERROR_OK;
+}
+
+/* flash bank str9x <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(str9x_flash_bank_command)
+{
+ struct str9x_flash_bank *str9x_info;
+
+ if (CMD_ARGC < 6)
+ {
+ LOG_WARNING("incomplete flash_bank str9x configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ str9x_info = malloc(sizeof(struct str9x_flash_bank));
+ bank->driver_priv = str9x_info;
+
+ str9x_build_block_list(bank);
+
+ str9x_info->write_algorithm = NULL;
+
+ return ERROR_OK;
+}
+
+static int str9x_protect_check(struct flash_bank *bank)
+{
+ int retval;
+ struct str9x_flash_bank *str9x_info = bank->driver_priv;
+ struct target *target = bank->target;
+
+ int i;
+ uint32_t adr;
+ uint32_t status = 0;
+ uint16_t hstatus = 0;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* read level one protection */
+
+ if (str9x_info->variant)
+ {
+ if (str9x_info->bank1)
+ {
+ adr = bank1start + 0x18;
+ if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
+ {
+ return retval;
+ }
+ status = hstatus;
+ }
+ else
+ {
+ adr = bank1start + 0x14;
+ if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_read_u32(target, adr, &status)) != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ }
+ else
+ {
+ adr = bank1start + 0x10;
+ if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
+ {
+ return retval;
+ }
+ status = hstatus;
+ }
+
+ /* read array command */
+ if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ if (status & str9x_info->sector_bits[i])
+ bank->sectors[i].is_protected = 1;
+ else
+ bank->sectors[i].is_protected = 0;
+ }
+
+ return ERROR_OK;
+}
+
+static int str9x_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ int i;
+ uint32_t adr;
+ uint8_t status;
+ uint8_t erase_cmd;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Check if we erase whole bank */
+ if ((first == 0) && (last == (bank->num_sectors - 1)))
+ {
+ /* Optimize to run erase bank command instead of sector */
+ erase_cmd = 0x80;
+ }
+ else
+ {
+ /* Erase sector command */
+ erase_cmd = 0x20;
+ }
+
+ for (i = first; i <= last; i++)
+ {
+ int retval;
+ adr = bank->base + bank->sectors[i].offset;
+
+ /* erase sectors */
+ if ((retval = target_write_u16(target, adr, erase_cmd)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = target_write_u16(target, adr, 0xD0)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ /* get status */
+ if ((retval = target_write_u16(target, adr, 0x70)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ int timeout;
+ for (timeout = 0; timeout < 1000; timeout++) {
+ if ((retval = target_read_u8(target, adr, &status)) != ERROR_OK)
+ {
+ return retval;
+ }
+ if (status & 0x80)
+ break;
+ alive_sleep(1);
+ }
+ if (timeout == 1000)
+ {
+ LOG_ERROR("erase timed out");
+ return ERROR_FAIL;
+ }
+
+ /* clear status, also clear read array */
+ if ((retval = target_write_u16(target, adr, 0x50)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ /* read array command */
+ if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (status & 0x22)
+ {
+ LOG_ERROR("error erasing flash bank, status: 0x%x", status);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* If we ran erase bank command, we are finished */
+ if (erase_cmd == 0x80)
+ break;
+ }
+
+ for (i = first; i <= last; i++)
+ bank->sectors[i].is_erased = 1;
+
+ return ERROR_OK;
+}
+
+static int str9x_protect(struct flash_bank *bank,
+ int set, int first, int last)
+{
+ struct target *target = bank->target;
+ int i;
+ uint32_t adr;
+ uint8_t status;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ for (i = first; i <= last; i++)
+ {
+ /* Level One Protection */
+
+ adr = bank->base + bank->sectors[i].offset;
+
+ target_write_u16(target, adr, 0x60);
+ if (set)
+ target_write_u16(target, adr, 0x01);
+ else
+ target_write_u16(target, adr, 0xD0);
+
+ /* query status */
+ target_read_u8(target, adr, &status);
+
+ /* clear status, also clear read array */
+ target_write_u16(target, adr, 0x50);
+
+ /* read array command */
+ target_write_u16(target, adr, 0xFF);
+ }
+
+ return ERROR_OK;
+}
+
+static int str9x_write_block(struct flash_bank *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct str9x_flash_bank *str9x_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t buffer_size = 8192;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[4];
+ struct armv4_5_algorithm armv4_5_info;
+ int retval = ERROR_OK;
+
+ uint32_t str9x_flash_write_code[] = {
+ /* write: */
+ 0xe3c14003, /* bic r4, r1, #3 */
+ 0xe3a03040, /* mov r3, #0x40 */
+ 0xe1c430b0, /* strh r3, [r4, #0] */
+ 0xe0d030b2, /* ldrh r3, [r0], #2 */
+ 0xe0c130b2, /* strh r3, [r1], #2 */
+ 0xe3a03070, /* mov r3, #0x70 */
+ 0xe1c430b0, /* strh r3, [r4, #0] */
+ /* busy: */
+ 0xe5d43000, /* ldrb r3, [r4, #0] */
+ 0xe3130080, /* tst r3, #0x80 */
+ 0x0afffffc, /* beq busy */
+ 0xe3a05050, /* mov r5, #0x50 */
+ 0xe1c450b0, /* strh r5, [r4, #0] */
+ 0xe3a050ff, /* mov r5, #0xFF */
+ 0xe1c450b0, /* strh r5, [r4, #0] */
+ 0xe3130012, /* tst r3, #0x12 */
+ 0x1a000001, /* bne exit */
+ 0xe2522001, /* subs r2, r2, #1 */
+ 0x1affffed, /* bne write */
+ /* exit: */
+ 0xeafffffe, /* b exit */
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
+ {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ };
+
+ target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
+
+ /* memory buffer */
+ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ {
+ buffer_size /= 2;
+ if (buffer_size <= 256)
+ {
+ /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+ if (str9x_info->write_algorithm)
+ target_free_working_area(target, str9x_info->write_algorithm);
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r3", 32, PARAM_IN);
+
+ while (count > 0)
+ {
+ uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
+
+ target_write_buffer(target, source->address, thisrun_count * 2, buffer);
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+
+ if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
+ {
+ LOG_ERROR("error executing str9x flash write algorithm");
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
+ {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += thisrun_count * 2;
+ address += thisrun_count * 2;
+ count -= thisrun_count;
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, str9x_info->write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+
+ return retval;
+}
+
+static int str9x_write(struct flash_bank *bank,
+ uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t words_remaining = (count / 2);
+ uint32_t bytes_remaining = (count & 0x00000001);
+ uint32_t address = bank->base + offset;
+ uint32_t bytes_written = 0;
+ uint8_t status;
+ int retval;
+ uint32_t check_address = offset;
+ uint32_t bank_adr;
+ int i;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x1)
+ {
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ uint32_t sec_start = bank->sectors[i].offset;
+ uint32_t sec_end = sec_start + bank->sectors[i].size;
+
+ /* check if destination falls within the current sector */
+ if ((check_address >= sec_start) && (check_address < sec_end))
+ {
+ /* check if destination ends in the current sector */
+ if (offset + count < sec_end)
+ check_address = offset + count;
+ else
+ check_address = sec_end;
+ }
+ }
+
+ if (check_address != offset + count)
+ return ERROR_FLASH_DST_OUT_OF_BANK;
+
+ /* multiple half words (2-byte) to be programmed? */
+ if (words_remaining > 0)
+ {
+ /* try using a block write */
+ if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
+ {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+ {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single dword accesses */
+ LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+ }
+ else if (retval == ERROR_FLASH_OPERATION_FAILED)
+ {
+ LOG_ERROR("flash writing failed with error code: 0x%x", retval);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ }
+ else
+ {
+ buffer += words_remaining * 2;
+ address += words_remaining * 2;
+ words_remaining = 0;
+ }
+ }
+
+ while (words_remaining > 0)
+ {
+ bank_adr = address & ~0x03;
+
+ /* write data command */
+ target_write_u16(target, bank_adr, 0x40);
+ target_write_memory(target, address, 2, 1, buffer + bytes_written);
+
+ /* get status command */
+ target_write_u16(target, bank_adr, 0x70);
+
+ int timeout;
+ for (timeout = 0; timeout < 1000; timeout++)
+ {
+ target_read_u8(target, bank_adr, &status);
+ if (status & 0x80)
+ break;
+ alive_sleep(1);
+ }
+ if (timeout == 1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
+ }
+
+ /* clear status reg and read array */
+ target_write_u16(target, bank_adr, 0x50);
+ target_write_u16(target, bank_adr, 0xFF);
+
+ if (status & 0x10)
+ return ERROR_FLASH_OPERATION_FAILED;
+ else if (status & 0x02)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ bytes_written += 2;
+ words_remaining--;
+ address += 2;
+ }
+
+ if (bytes_remaining)
+ {
+ uint8_t last_halfword[2] = {0xff, 0xff};
+ int i = 0;
+
+ while (bytes_remaining > 0)
+ {
+ last_halfword[i++] = *(buffer + bytes_written);
+ bytes_remaining--;
+ bytes_written++;
+ }
+
+ bank_adr = address & ~0x03;
+
+ /* write data command */
+ target_write_u16(target, bank_adr, 0x40);
+ target_write_memory(target, address, 2, 1, last_halfword);
+
+ /* query status command */
+ target_write_u16(target, bank_adr, 0x70);
+
+ int timeout;
+ for (timeout = 0; timeout < 1000; timeout++)
+ {
+ target_read_u8(target, bank_adr, &status);
+ if (status & 0x80)
+ break;
+ alive_sleep(1);
+ }
+ if (timeout == 1000)
+ {
+ LOG_ERROR("write timed out");
+ return ERROR_FAIL;
+ }
+
+ /* clear status reg and read array */
+ target_write_u16(target, bank_adr, 0x50);
+ target_write_u16(target, bank_adr, 0xFF);
+
+ if (status & 0x10)
+ return ERROR_FLASH_OPERATION_FAILED;
+ else if (status & 0x02)
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+static int str9x_probe(struct flash_bank *bank)
+{
+ return ERROR_OK;
+}
+
+#if 0
+COMMAND_HANDLER(str9x_handle_part_id_command)
+{
+ return ERROR_OK;
+}
+#endif
+
+static int str9x_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ snprintf(buf, buf_size, "str9x flash driver info");
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(str9x_handle_flash_config_command)
+{
+ struct str9x_flash_bank *str9x_info;
+ struct target *target = NULL;
+
+ if (CMD_ARGC < 5)
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ uint32_t bbsr, nbbsr, bbadr, nbbadr;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], bbsr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], nbbsr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], bbadr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], nbbadr);
+
+ str9x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* config flash controller */
+ target_write_u32(target, FLASH_BBSR, bbsr);
+ target_write_u32(target, FLASH_NBBSR, nbbsr);
+ target_write_u32(target, FLASH_BBADR, bbadr >> 2);
+ target_write_u32(target, FLASH_NBBADR, nbbadr >> 2);
+
+ /* set bit 18 instruction TCM order as per flash programming manual */
+ arm966e_write_cp15(target, 62, 0x40000);
+
+ /* enable flash bank 1 */
+ target_write_u32(target, FLASH_CR, 0x18);
+ return ERROR_OK;
+}
+
+static int str9x_register_commands(struct command_context *cmd_ctx)
+{
+ struct command *str9x_cmd = register_command(cmd_ctx, NULL, "str9x",
+ NULL, COMMAND_ANY, "str9x flash commands");
+
+ register_command(cmd_ctx, str9x_cmd, "flash_config",
+ str9x_handle_flash_config_command, COMMAND_EXEC,
+ "configure str9 flash controller");
+
+ return ERROR_OK;
+}
+
+struct flash_driver str9x_flash = {
+ .name = "str9x",
+ .register_commands = &str9x_register_commands,
+ .flash_bank_command = &str9x_flash_bank_command,
+ .erase = &str9x_erase,
+ .protect = &str9x_protect,
+ .write = &str9x_write,
+ .probe = &str9x_probe,
+ .auto_probe = &str9x_probe,
+ .erase_check = &default_flash_blank_check,
+ .protect_check = &str9x_protect_check,
+ .info = &str9x_info,
+ };
Code Review / openocd.git / blobdiff