-/***************************************************************************\r
- * Copyright (C) 2005 by Dominic Rath *\r
- * Dominic.Rath@gmx.de *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "replacements.h"\r
-\r
-#include "stm32x.h"\r
-#include "flash.h"\r
-#include "target.h"\r
-#include "log.h"\r
-#include "armv7m.h"\r
-#include "algorithm.h"\r
-#include "binarybuffer.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-int stm32x_register_commands(struct command_context_s *cmd_ctx);\r
-int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
-int stm32x_erase(struct flash_bank_s *bank, int first, int last);\r
-int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);\r
-int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
-int stm32x_probe(struct flash_bank_s *bank);\r
-int stm32x_auto_probe(struct flash_bank_s *bank);\r
-int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int stm32x_protect_check(struct flash_bank_s *bank);\r
-int stm32x_erase_check(struct flash_bank_s *bank);\r
-int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
-\r
-int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-\r
-flash_driver_t stm32x_flash =\r
-{\r
- .name = "stm32x",\r
- .register_commands = stm32x_register_commands,\r
- .flash_bank_command = stm32x_flash_bank_command,\r
- .erase = stm32x_erase,\r
- .protect = stm32x_protect,\r
- .write = stm32x_write,\r
- .probe = stm32x_probe,\r
- .auto_probe = stm32x_auto_probe,\r
- .erase_check = stm32x_erase_check,\r
- .protect_check = stm32x_protect_check,\r
- .info = stm32x_info\r
-};\r
-\r
-int stm32x_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");\r
- \r
- register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,\r
- "lock device");\r
- register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,\r
- "unlock protected device");\r
- register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,\r
- "mass erase device");\r
- register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,\r
- "read device option bytes");\r
- register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,\r
- "write device option bytes");\r
- return ERROR_OK;\r
-}\r
-\r
-/* flash bank stm32x <base> <size> 0 0 <target#>\r
- */\r
-int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
-{\r
- stm32x_flash_bank_t *stm32x_info;\r
- \r
- if (argc < 6)\r
- {\r
- WARNING("incomplete flash_bank stm32x configuration");\r
- return ERROR_FLASH_BANK_INVALID;\r
- }\r
- \r
- stm32x_info = malloc(sizeof(stm32x_flash_bank_t));\r
- bank->driver_priv = stm32x_info;\r
- \r
- stm32x_info->write_algorithm = NULL;\r
- stm32x_info->probed = 0;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-u32 stm32x_get_flash_status(flash_bank_t *bank)\r
-{\r
- target_t *target = bank->target;\r
- u32 status;\r
- \r
- target_read_u32(target, STM32_FLASH_SR, &status);\r
- \r
- return status;\r
-}\r
-\r
-u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)\r
-{\r
- u32 status;\r
- \r
- /* wait for busy to clear */\r
- while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))\r
- {\r
- DEBUG("status: 0x%x", status);\r
- usleep(1000);\r
- }\r
- \r
- return status;\r
-}\r
-\r
-int stm32x_read_options(struct flash_bank_s *bank)\r
-{\r
- u32 optiondata;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- target_t *target = bank->target;\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- /* read current option bytes */\r
- target_read_u32(target, STM32_FLASH_OBR, &optiondata);\r
- \r
- stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);\r
- stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;\r
- \r
- if (optiondata & (1 << OPT_READOUT))\r
- INFO("Device Security Bit Set");\r
- \r
- /* each bit refers to a 4bank protection */\r
- target_read_u32(target, STM32_FLASH_WRPR, &optiondata);\r
- \r
- stm32x_info->option_bytes.protection[0] = (u16)optiondata;\r
- stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);\r
- stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);\r
- stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_erase_options(struct flash_bank_s *bank)\r
-{\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- target_t *target = bank->target;\r
- u32 status;\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- /* read current options */\r
- stm32x_read_options(bank);\r
- \r
- /* unlock flash registers */\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
- \r
- /* unlock option flash registers */\r
- target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);\r
- \r
- /* erase option bytes */\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* clear readout protection and complementary option bytes\r
- * this will also force a device unlock if set */\r
- stm32x_info->option_bytes.RDP = 0x5AA5;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_write_options(struct flash_bank_s *bank)\r
-{\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- target_t *target = bank->target;\r
- u32 status;\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- /* unlock flash registers */\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
- \r
- /* unlock option flash registers */\r
- target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);\r
- \r
- /* program option bytes */\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);\r
- \r
- /* write user option byte */\r
- target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* write protection byte 1 */\r
- target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* write protection byte 2 */\r
- target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* write protection byte 3 */\r
- target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* write protection byte 4 */\r
- target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- /* write readout protection bit */\r
- target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- \r
- target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- u8 *buffer;\r
- int i;\r
- int nBytes;\r
- \r
- if ((first < 0) || (last > bank->num_sectors))\r
- return ERROR_FLASH_SECTOR_INVALID;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- buffer = malloc(256);\r
- \r
- for (i = first; i <= last; i++)\r
- {\r
- bank->sectors[i].is_erased = 1;\r
-\r
- target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);\r
- \r
- for (nBytes = 0; nBytes < 256; nBytes++)\r
- {\r
- if (buffer[nBytes] != 0xFF)\r
- {\r
- bank->sectors[i].is_erased = 0;\r
- break;\r
- }\r
- } \r
- }\r
- \r
- free(buffer);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_protect_check(struct flash_bank_s *bank)\r
-{\r
- target_t *target = bank->target;\r
- \r
- u32 protection;\r
- int i, s;\r
- int num_bits;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- /* each bit refers to a 4bank protection */\r
- target_read_u32(target, STM32_FLASH_WRPR, &protection);\r
- \r
- /* each protection bit is for 4 1K pages */\r
- num_bits = (bank->num_sectors / 4);\r
- \r
- for (i = 0; i < num_bits; i++)\r
- {\r
- int set = 1;\r
- \r
- if( protection & (1 << i))\r
- set = 0;\r
- \r
- for (s = 0; s < 4; s++)\r
- bank->sectors[(i * 4) + s].is_protected = set;\r
- }\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_erase(struct flash_bank_s *bank, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- \r
- int i;\r
- u32 status;\r
- \r
- /* unlock flash registers */\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
- \r
- for (i = first; i <= last; i++)\r
- { \r
- target_write_u32(target, STM32_FLASH_CR, FLASH_PER);\r
- target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- bank->sectors[i].is_erased = 1;\r
- }\r
-\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)\r
-{\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- target_t *target = bank->target;\r
- u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};\r
- int i, reg, bit;\r
- int status;\r
- u32 protection;\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))\r
- {\r
- WARNING("sector start/end incorrect - stm32 has 4K sector protection");\r
- return ERROR_FLASH_SECTOR_INVALID;\r
- }\r
- \r
- /* each bit refers to a 4bank protection */\r
- target_read_u32(target, STM32_FLASH_WRPR, &protection);\r
- \r
- prot_reg[0] = (u16)protection;\r
- prot_reg[1] = (u16)(protection >> 8);\r
- prot_reg[2] = (u16)(protection >> 16);\r
- prot_reg[3] = (u16)(protection >> 24);\r
- \r
- for (i = first; i <= last; i++)\r
- {\r
- reg = (i / 4) / 8;\r
- bit = (i / 4) - (reg * 8);\r
- \r
- if( set )\r
- prot_reg[reg] &= ~(1 << bit);\r
- else\r
- prot_reg[reg] |= (1 << bit);\r
- }\r
- \r
- if ((status = stm32x_erase_options(bank)) != ERROR_OK)\r
- return status;\r
- \r
- stm32x_info->option_bytes.protection[0] = prot_reg[0];\r
- stm32x_info->option_bytes.protection[1] = prot_reg[1];\r
- stm32x_info->option_bytes.protection[2] = prot_reg[2];\r
- stm32x_info->option_bytes.protection[3] = prot_reg[3];\r
- \r
- return stm32x_write_options(bank);\r
-}\r
-\r
-int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
- target_t *target = bank->target;\r
- u32 buffer_size = 8192;\r
- working_area_t *source;\r
- u32 address = bank->base + offset;\r
- reg_param_t reg_params[4];\r
- armv7m_algorithm_t armv7m_info;\r
- int retval = ERROR_OK;\r
- \r
- u8 stm32x_flash_write_code[] = {\r
- /* write: */\r
- 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */\r
- 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */\r
- 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */\r
- 0x23, 0x60, /* str r3, [r4, #0] */\r
- 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */\r
- 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */\r
- /* busy: */\r
- 0x2B, 0x68, /* ldr r3, [r5, #0] */\r
- 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */\r
- 0xFB, 0xD0, /* beq busy */\r
- 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */\r
- 0x01, 0xD1, /* bne exit */\r
- 0x01, 0x3A, /* subs r2, r2, #1 */\r
- 0xED, 0xD1, /* bne write */\r
- /* exit: */\r
- 0xFE, 0xE7, /* b exit */ \r
- 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */\r
- 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */\r
- };\r
- \r
- /* flash write code */\r
- if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)\r
- {\r
- WARNING("no working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- };\r
- \r
- target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);\r
-\r
- /* memory buffer */\r
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)\r
- {\r
- buffer_size /= 2;\r
- if (buffer_size <= 256)\r
- {\r
- /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */\r
- if (stm32x_info->write_algorithm)\r
- target_free_working_area(target, stm32x_info->write_algorithm);\r
- \r
- WARNING("no large enough working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- }\r
- };\r
- \r
- armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;\r
- armv7m_info.core_mode = ARMV7M_MODE_ANY;\r
- armv7m_info.core_state = ARMV7M_STATE_THUMB;\r
- \r
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT);\r
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);\r
- init_reg_param(®_params[2], "r2", 32, PARAM_OUT);\r
- init_reg_param(®_params[3], "r3", 32, PARAM_IN);\r
- \r
- while (count > 0)\r
- {\r
- u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;\r
- \r
- target_write_buffer(target, source->address, thisrun_count * 2, buffer);\r
- \r
- buf_set_u32(reg_params[0].value, 0, 32, source->address);\r
- buf_set_u32(reg_params[1].value, 0, 32, address);\r
- buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);\r
- \r
- if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \\r
- stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)\r
- {\r
- ERROR("error executing str7x flash write algorithm");\r
- break;\r
- }\r
- \r
- if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)\r
- {\r
- retval = ERROR_FLASH_OPERATION_FAILED;\r
- break;\r
- }\r
- \r
- buffer += thisrun_count * 2;\r
- address += thisrun_count * 2;\r
- count -= thisrun_count;\r
- }\r
- \r
- target_free_working_area(target, source);\r
- target_free_working_area(target, stm32x_info->write_algorithm);\r
- \r
- destroy_reg_param(®_params[0]);\r
- destroy_reg_param(®_params[1]);\r
- destroy_reg_param(®_params[2]);\r
- destroy_reg_param(®_params[3]);\r
- \r
- return retval;\r
-}\r
-\r
-int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- target_t *target = bank->target;\r
- u32 words_remaining = (count / 2);\r
- u32 bytes_remaining = (count & 0x00000001);\r
- u32 address = bank->base + offset;\r
- u32 bytes_written = 0;\r
- u8 status;\r
- u32 retval;\r
- \r
- if (offset & 0x1)\r
- {\r
- WARNING("offset 0x%x breaks required 2-byte alignment", offset);\r
- return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
- }\r
- \r
- /* unlock flash registers */\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
- \r
- /* multiple half words (2-byte) to be programmed? */\r
- if (words_remaining > 0) \r
- {\r
- /* try using a block write */\r
- if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)\r
- {\r
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)\r
- {\r
- /* if block write failed (no sufficient working area),\r
- * we use normal (slow) single dword accesses */ \r
- WARNING("couldn't use block writes, falling back to single memory accesses");\r
- }\r
- else if (retval == ERROR_FLASH_OPERATION_FAILED)\r
- {\r
- ERROR("flash writing failed with error code: 0x%x", retval);\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- }\r
- else\r
- {\r
- buffer += words_remaining * 2;\r
- address += words_remaining * 2;\r
- words_remaining = 0;\r
- }\r
- }\r
-\r
- while (words_remaining > 0)\r
- {\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_PG);\r
- target_write_u16(target, address, *(u16*)(buffer + bytes_written));\r
- \r
- status = stm32x_wait_status_busy(bank, 5);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
-\r
- bytes_written += 2;\r
- words_remaining--;\r
- address += 2;\r
- }\r
- \r
- if (bytes_remaining)\r
- {\r
- u8 last_halfword[2] = {0xff, 0xff};\r
- int i = 0;\r
- \r
- while(bytes_remaining > 0)\r
- {\r
- last_halfword[i++] = *(buffer + bytes_written); \r
- bytes_remaining--;\r
- bytes_written++;\r
- }\r
- \r
- target_write_u32(target, STM32_FLASH_CR, FLASH_PG);\r
- target_write_u16(target, address, *(u16*)last_halfword);\r
- \r
- status = stm32x_wait_status_busy(bank, 5);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & FLASH_PGERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- \r
- target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_probe(struct flash_bank_s *bank)\r
-{\r
- target_t *target = bank->target;\r
- stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
- int i;\r
- u16 num_sectors;\r
- u32 device_id;\r
- \r
- stm32x_info->probed = 0;\r
- \r
- /* read stm32 device id register */\r
- target_read_u32(target, 0xE0042000, &device_id);\r
- INFO( "device id = 0x%08x", device_id );\r
- \r
- if (!(device_id & 0x410))\r
- {\r
- WARNING( "Cannot identify target as a STM32 family." );\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- \r
- /* get flash size from target */\r
- target_read_u16(target, 0x1FFFF7E0, &num_sectors);\r
- \r
- /* check for early silicon rev A */\r
- if ((device_id >> 16) == 0 )\r
- {\r
- /* number of sectors incorrect on revA */\r
- WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );\r
- num_sectors = 128;\r
- }\r
- \r
- INFO( "flash size = %dkbytes", num_sectors );\r
- \r
- bank->base = 0x08000000;\r
- bank->size = num_sectors * 1024;\r
- bank->num_sectors = num_sectors;\r
- bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);\r
- \r
- for (i = 0; i < num_sectors; i++)\r
- {\r
- bank->sectors[i].offset = i * 1024;\r
- bank->sectors[i].size = 1024;\r
- bank->sectors[i].is_erased = -1;\r
- bank->sectors[i].is_protected = 1;\r
- }\r
- \r
- stm32x_info->probed = 1;\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_auto_probe(struct flash_bank_s *bank)\r
-{\r
- stm32x_flash_bank_t *stm32x_info = bank->driver_priv;\r
- if (stm32x_info->probed)\r
- return ERROR_OK;\r
- return stm32x_probe(bank);\r
-}\r
-\r
-int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_erase_check(struct flash_bank_s *bank)\r
-{\r
- return stm32x_blank_check(bank, 0, bank->num_sectors - 1);\r
-}\r
-\r
-int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
-{\r
- snprintf(buf, buf_size, "stm32x flash driver info" );\r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- \r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "stm32x lock <bank>");\r
- return ERROR_OK; \r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- if (stm32x_erase_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to erase options");\r
- return ERROR_OK;\r
- }\r
- \r
- /* set readout protection */ \r
- stm32x_info->option_bytes.RDP = 0;\r
- \r
- if (stm32x_write_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to lock device");\r
- return ERROR_OK;\r
- }\r
- \r
- command_print(cmd_ctx, "stm32x locked");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- \r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "stm32x unlock <bank>");\r
- return ERROR_OK; \r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- if (stm32x_erase_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to unlock device");\r
- return ERROR_OK;\r
- }\r
- \r
- if (stm32x_write_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to lock device");\r
- return ERROR_OK;\r
- }\r
- \r
- command_print(cmd_ctx, "stm32x unlocked");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- u32 optionbyte;\r
- target_t *target = NULL;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- \r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "stm32x options_read <bank>");\r
- return ERROR_OK; \r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- target_read_u32(target, STM32_FLASH_OBR, &optionbyte);\r
- command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);\r
- \r
- if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))\r
- command_print(cmd_ctx, "Option Byte Complement Error");\r
- \r
- if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))\r
- command_print(cmd_ctx, "Readout Protection On");\r
- else\r
- command_print(cmd_ctx, "Readout Protection Off");\r
- \r
- if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))\r
- command_print(cmd_ctx, "Software Watchdog");\r
- else\r
- command_print(cmd_ctx, "Hardware Watchdog");\r
- \r
- if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))\r
- command_print(cmd_ctx, "Stop: No reset generated");\r
- else\r
- command_print(cmd_ctx, "Stop: Reset generated");\r
- \r
- if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))\r
- command_print(cmd_ctx, "Standby: No reset generated");\r
- else\r
- command_print(cmd_ctx, "Standby: Reset generated");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- u16 optionbyte = 0xF8;\r
- \r
- if (argc < 4)\r
- {\r
- command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");\r
- return ERROR_OK; \r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- if (strcmp(args[1], "SWWDG") == 0)\r
- {\r
- optionbyte |= (1<<0);\r
- }\r
- else\r
- {\r
- optionbyte &= ~(1<<0);\r
- }\r
- \r
- if (strcmp(args[2], "NORSTSTNDBY") == 0)\r
- {\r
- optionbyte |= (1<<1);\r
- }\r
- else\r
- {\r
- optionbyte &= ~(1<<1);\r
- }\r
- \r
- if (strcmp(args[3], "NORSTSTOP") == 0)\r
- {\r
- optionbyte |= (1<<2);\r
- }\r
- else\r
- {\r
- optionbyte &= ~(1<<2);\r
- }\r
- \r
- if (stm32x_erase_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to erase options");\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info->option_bytes.user_options = optionbyte;\r
- \r
- if (stm32x_write_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "stm32x failed to write options");\r
- return ERROR_OK;\r
- }\r
- \r
- command_print(cmd_ctx, "stm32x write options complete");\r
- \r
- return ERROR_OK;\r
-}\r
-\r
-int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- target_t *target = NULL;\r
- stm32x_flash_bank_t *stm32x_info = NULL;\r
- flash_bank_t *bank;\r
- u32 status;\r
- \r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "stm32x mass_erase <bank>");\r
- return ERROR_OK; \r
- }\r
- \r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
- \r
- stm32x_info = bank->driver_priv;\r
- \r
- target = bank->target;\r
- \r
- if (target->state != TARGET_HALTED)\r
- {\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
- \r
- /* unlock option flash registers */\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY1);\r
- target_write_u32(target, STM32_FLASH_KEYR, KEY2);\r
- \r
- /* mass erase flash memory */\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_MER);\r
- target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);\r
- \r
- status = stm32x_wait_status_busy(bank, 10);\r
- \r
- target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);\r
- \r
- if( status & FLASH_WRPRTERR )\r
- {\r
- command_print(cmd_ctx, "stm32x device protected");\r
- return ERROR_OK;\r
- }\r
- \r
- if( status & FLASH_PGERR )\r
- {\r
- command_print(cmd_ctx, "stm32x device programming failed");\r
- return ERROR_OK;\r
- }\r
- \r
- command_print(cmd_ctx, "stm32x mass erase complete");\r
- \r
- return ERROR_OK;\r
-}\r
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "stm32x.h"
+#include "flash.h"
+#include "target.h"
+#include "log.h"
+#include "armv7m.h"
+#include "algorithm.h"
+#include "binarybuffer.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+int stm32x_register_commands(struct command_context_s *cmd_ctx);
+int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+int stm32x_erase(struct flash_bank_s *bank, int first, int last);
+int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
+int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+int stm32x_probe(struct flash_bank_s *bank);
+int stm32x_auto_probe(struct flash_bank_s *bank);
+int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int stm32x_protect_check(struct flash_bank_s *bank);
+int stm32x_erase_check(struct flash_bank_s *bank);
+int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
+
+int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+flash_driver_t stm32x_flash =
+{
+ .name = "stm32x",
+ .register_commands = stm32x_register_commands,
+ .flash_bank_command = stm32x_flash_bank_command,
+ .erase = stm32x_erase,
+ .protect = stm32x_protect,
+ .write = stm32x_write,
+ .probe = stm32x_probe,
+ .auto_probe = stm32x_auto_probe,
+ .erase_check = stm32x_erase_check,
+ .protect_check = stm32x_protect_check,
+ .info = stm32x_info
+};
+
+int stm32x_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
+
+ register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
+ "lock device");
+ register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
+ "unlock protected device");
+ register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
+ "mass erase device");
+ register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
+ "read device option bytes");
+ register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
+ "write device option bytes");
+ return ERROR_OK;
+}
+
+/* flash bank stm32x <base> <size> 0 0 <target#>
+ */
+int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+{
+ stm32x_flash_bank_t *stm32x_info;
+
+ if (argc < 6)
+ {
+ WARNING("incomplete flash_bank stm32x configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
+ bank->driver_priv = stm32x_info;
+
+ stm32x_info->write_algorithm = NULL;
+ stm32x_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+u32 stm32x_get_flash_status(flash_bank_t *bank)
+{
+ target_t *target = bank->target;
+ u32 status;
+
+ target_read_u32(target, STM32_FLASH_SR, &status);
+
+ return status;
+}
+
+u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
+{
+ u32 status;
+
+ /* wait for busy to clear */
+ while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
+ {
+ DEBUG("status: 0x%x", status);
+ usleep(1000);
+ }
+
+ return status;
+}
+
+int stm32x_read_options(struct flash_bank_s *bank)
+{
+ u32 optiondata;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ target_t *target = bank->target;
+
+ stm32x_info = bank->driver_priv;
+
+ /* read current option bytes */
+ target_read_u32(target, STM32_FLASH_OBR, &optiondata);
+
+ stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
+ stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
+
+ if (optiondata & (1 << OPT_READOUT))
+ INFO("Device Security Bit Set");
+
+ /* each bit refers to a 4bank protection */
+ target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
+
+ stm32x_info->option_bytes.protection[0] = (u16)optiondata;
+ stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
+ stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
+ stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
+
+ return ERROR_OK;
+}
+
+int stm32x_erase_options(struct flash_bank_s *bank)
+{
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ target_t *target = bank->target;
+ u32 status;
+
+ stm32x_info = bank->driver_priv;
+
+ /* read current options */
+ stm32x_read_options(bank);
+
+ /* unlock flash registers */
+ target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+
+ /* unlock option flash registers */
+ target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
+
+ /* erase option bytes */
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* clear readout protection and complementary option bytes
+ * this will also force a device unlock if set */
+ stm32x_info->option_bytes.RDP = 0x5AA5;
+
+ return ERROR_OK;
+}
+
+int stm32x_write_options(struct flash_bank_s *bank)
+{
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ target_t *target = bank->target;
+ u32 status;
+
+ stm32x_info = bank->driver_priv;
+
+ /* unlock flash registers */
+ target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+
+ /* unlock option flash registers */
+ target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
+
+ /* program option bytes */
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
+
+ /* write user option byte */
+ target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* write protection byte 1 */
+ target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* write protection byte 2 */
+ target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* write protection byte 3 */
+ target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* write protection byte 4 */
+ target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* write readout protection bit */
+ target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+
+ return ERROR_OK;
+}
+
+int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
+{
+ target_t *target = bank->target;
+ u8 *buffer;
+ int i;
+ int nBytes;
+
+ if ((first < 0) || (last > bank->num_sectors))
+ return ERROR_FLASH_SECTOR_INVALID;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ buffer = malloc(256);
+
+ for (i = first; i <= last; i++)
+ {
+ bank->sectors[i].is_erased = 1;
+
+ target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
+
+ for (nBytes = 0; nBytes < 256; nBytes++)
+ {
+ if (buffer[nBytes] != 0xFF)
+ {
+ bank->sectors[i].is_erased = 0;
+ break;
+ }
+ }
+ }
+
+ free(buffer);
+
+ return ERROR_OK;
+}
+
+int stm32x_protect_check(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+
+ u32 protection;
+ int i, s;
+ int num_bits;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* each bit refers to a 4bank protection */
+ target_read_u32(target, STM32_FLASH_WRPR, &protection);
+
+ /* each protection bit is for 4 1K pages */
+ num_bits = (bank->num_sectors / 4);
+
+ for (i = 0; i < num_bits; i++)
+ {
+ int set = 1;
+
+ if( protection & (1 << i))
+ set = 0;
+
+ for (s = 0; s < 4; s++)
+ bank->sectors[(i * 4) + s].is_protected = set;
+ }
+
+ return ERROR_OK;
+}
+
+int stm32x_erase(struct flash_bank_s *bank, int first, int last)
+{
+ target_t *target = bank->target;
+
+ int i;
+ u32 status;
+
+ /* unlock flash registers */
+ target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+
+ for (i = first; i <= last; i++)
+ {
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
+ target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ bank->sectors[i].is_erased = 1;
+ }
+
+ target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+
+ return ERROR_OK;
+}
+
+int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ target_t *target = bank->target;
+ u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+ int i, reg, bit;
+ int status;
+ u32 protection;
+
+ stm32x_info = bank->driver_priv;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
+ {
+ WARNING("sector start/end incorrect - stm32 has 4K sector protection");
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ /* each bit refers to a 4bank protection */
+ target_read_u32(target, STM32_FLASH_WRPR, &protection);
+
+ prot_reg[0] = (u16)protection;
+ prot_reg[1] = (u16)(protection >> 8);
+ prot_reg[2] = (u16)(protection >> 16);
+ prot_reg[3] = (u16)(protection >> 24);
+
+ for (i = first; i <= last; i++)
+ {
+ reg = (i / 4) / 8;
+ bit = (i / 4) - (reg * 8);
+
+ if( set )
+ prot_reg[reg] &= ~(1 << bit);
+ else
+ prot_reg[reg] |= (1 << bit);
+ }
+
+ if ((status = stm32x_erase_options(bank)) != ERROR_OK)
+ return status;
+
+ stm32x_info->option_bytes.protection[0] = prot_reg[0];
+ stm32x_info->option_bytes.protection[1] = prot_reg[1];
+ stm32x_info->option_bytes.protection[2] = prot_reg[2];
+ stm32x_info->option_bytes.protection[3] = prot_reg[3];
+
+ return stm32x_write_options(bank);
+}
+
+int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
+ target_t *target = bank->target;
+ u32 buffer_size = 8192;
+ working_area_t *source;
+ u32 address = bank->base + offset;
+ reg_param_t reg_params[4];
+ armv7m_algorithm_t armv7m_info;
+ int retval = ERROR_OK;
+
+ u8 stm32x_flash_write_code[] = {
+ /* write: */
+ 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
+ 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
+ 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
+ 0x23, 0x60, /* str r3, [r4, #0] */
+ 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
+ 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
+ /* busy: */
+ 0x2B, 0x68, /* ldr r3, [r5, #0] */
+ 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
+ 0xFB, 0xD0, /* beq busy */
+ 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
+ 0x01, 0xD1, /* bne exit */
+ 0x01, 0x3A, /* subs r2, r2, #1 */
+ 0xED, 0xD1, /* bne write */
+ /* exit: */
+ 0xFE, 0xE7, /* b exit */
+ 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
+ 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
+ {
+ WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ };
+
+ target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
+
+ /* memory buffer */
+ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ {
+ buffer_size /= 2;
+ if (buffer_size <= 256)
+ {
+ /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+ if (stm32x_info->write_algorithm)
+ target_free_working_area(target, stm32x_info->write_algorithm);
+
+ WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ };
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARMV7M_MODE_ANY;
+ armv7m_info.core_state = ARMV7M_STATE_THUMB;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r3", 32, PARAM_IN);
+
+ while (count > 0)
+ {
+ u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
+
+ target_write_buffer(target, source->address, thisrun_count * 2, buffer);
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+
+ if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
+ stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
+ {
+ ERROR("error executing str7x flash write algorithm");
+ break;
+ }
+
+ if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
+ {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += thisrun_count * 2;
+ address += thisrun_count * 2;
+ count -= thisrun_count;
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, stm32x_info->write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+
+ return retval;
+}
+
+int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ target_t *target = bank->target;
+ u32 words_remaining = (count / 2);
+ u32 bytes_remaining = (count & 0x00000001);
+ u32 address = bank->base + offset;
+ u32 bytes_written = 0;
+ u8 status;
+ u32 retval;
+
+ if (offset & 0x1)
+ {
+ WARNING("offset 0x%x breaks required 2-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ /* unlock flash registers */
+ target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+
+ /* multiple half words (2-byte) to be programmed? */
+ if (words_remaining > 0)
+ {
+ /* try using a block write */
+ if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
+ {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+ {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single dword accesses */
+ WARNING("couldn't use block writes, falling back to single memory accesses");
+ }
+ else if (retval == ERROR_FLASH_OPERATION_FAILED)
+ {
+ ERROR("flash writing failed with error code: 0x%x", retval);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ }
+ else
+ {
+ buffer += words_remaining * 2;
+ address += words_remaining * 2;
+ words_remaining = 0;
+ }
+ }
+
+ while (words_remaining > 0)
+ {
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
+ target_write_u16(target, address, *(u16*)(buffer + bytes_written));
+
+ status = stm32x_wait_status_busy(bank, 5);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ bytes_written += 2;
+ words_remaining--;
+ address += 2;
+ }
+
+ if (bytes_remaining)
+ {
+ u8 last_halfword[2] = {0xff, 0xff};
+ int i = 0;
+
+ while(bytes_remaining > 0)
+ {
+ last_halfword[i++] = *(buffer + bytes_written);
+ bytes_remaining--;
+ bytes_written++;
+ }
+
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
+ target_write_u16(target, address, *(u16*)last_halfword);
+
+ status = stm32x_wait_status_busy(bank, 5);
+
+ if( status & FLASH_WRPRTERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ if( status & FLASH_PGERR )
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+
+ return ERROR_OK;
+}
+
+int stm32x_probe(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
+ int i;
+ u16 num_sectors;
+ u32 device_id;
+
+ stm32x_info->probed = 0;
+
+ /* read stm32 device id register */
+ target_read_u32(target, 0xE0042000, &device_id);
+ INFO( "device id = 0x%08x", device_id );
+
+ if (!(device_id & 0x410))
+ {
+ WARNING( "Cannot identify target as a STM32 family." );
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* get flash size from target */
+ target_read_u16(target, 0x1FFFF7E0, &num_sectors);
+
+ /* check for early silicon rev A */
+ if ((device_id >> 16) == 0 )
+ {
+ /* number of sectors incorrect on revA */
+ WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
+ num_sectors = 128;
+ }
+
+ INFO( "flash size = %dkbytes", num_sectors );
+
+ bank->base = 0x08000000;
+ bank->size = num_sectors * 1024;
+ bank->num_sectors = num_sectors;
+ bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
+
+ for (i = 0; i < num_sectors; i++)
+ {
+ bank->sectors[i].offset = i * 1024;
+ bank->sectors[i].size = 1024;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ stm32x_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+int stm32x_auto_probe(struct flash_bank_s *bank)
+{
+ stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
+ if (stm32x_info->probed)
+ return ERROR_OK;
+ return stm32x_probe(bank);
+}
+
+int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ return ERROR_OK;
+}
+
+int stm32x_erase_check(struct flash_bank_s *bank)
+{
+ return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
+}
+
+int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
+{
+ snprintf(buf, buf_size, "stm32x flash driver info" );
+ return ERROR_OK;
+}
+
+int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ target_t *target = NULL;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "stm32x lock <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ stm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (stm32x_erase_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to erase options");
+ return ERROR_OK;
+ }
+
+ /* set readout protection */
+ stm32x_info->option_bytes.RDP = 0;
+
+ if (stm32x_write_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "stm32x locked");
+
+ return ERROR_OK;
+}
+
+int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ target_t *target = NULL;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "stm32x unlock <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ stm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (stm32x_erase_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to unlock device");
+ return ERROR_OK;
+ }
+
+ if (stm32x_write_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "stm32x unlocked");
+
+ return ERROR_OK;
+}
+
+int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ u32 optionbyte;
+ target_t *target = NULL;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "stm32x options_read <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ stm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
+ command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
+
+ if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
+ command_print(cmd_ctx, "Option Byte Complement Error");
+
+ if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
+ command_print(cmd_ctx, "Readout Protection On");
+ else
+ command_print(cmd_ctx, "Readout Protection Off");
+
+ if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
+ command_print(cmd_ctx, "Software Watchdog");
+ else
+ command_print(cmd_ctx, "Hardware Watchdog");
+
+ if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
+ command_print(cmd_ctx, "Stop: No reset generated");
+ else
+ command_print(cmd_ctx, "Stop: Reset generated");
+
+ if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
+ command_print(cmd_ctx, "Standby: No reset generated");
+ else
+ command_print(cmd_ctx, "Standby: Reset generated");
+
+ return ERROR_OK;
+}
+
+int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ target_t *target = NULL;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ u16 optionbyte = 0xF8;
+
+ if (argc < 4)
+ {
+ command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ stm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (strcmp(args[1], "SWWDG") == 0)
+ {
+ optionbyte |= (1<<0);
+ }
+ else
+ {
+ optionbyte &= ~(1<<0);
+ }
+
+ if (strcmp(args[2], "NORSTSTNDBY") == 0)
+ {
+ optionbyte |= (1<<1);
+ }
+ else
+ {
+ optionbyte &= ~(1<<1);
+ }
+
+ if (strcmp(args[3], "NORSTSTOP") == 0)
+ {
+ optionbyte |= (1<<2);
+ }
+ else
+ {
+ optionbyte &= ~(1<<2);
+ }
+
+ if (stm32x_erase_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to erase options");
+ return ERROR_OK;
+ }
+
+ stm32x_info->option_bytes.user_options = optionbyte;
+
+ if (stm32x_write_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "stm32x failed to write options");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "stm32x write options complete");
+
+ return ERROR_OK;
+}
+
+int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = NULL;
+ stm32x_flash_bank_t *stm32x_info = NULL;
+ flash_bank_t *bank;
+ u32 status;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "stm32x mass_erase <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ stm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* unlock option flash registers */
+ target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+
+ /* mass erase flash memory */
+ target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
+
+ status = stm32x_wait_status_busy(bank, 10);
+
+ target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+
+ if( status & FLASH_WRPRTERR )
+ {
+ command_print(cmd_ctx, "stm32x device protected");
+ return ERROR_OK;
+ }
+
+ if( status & FLASH_PGERR )
+ {
+ command_print(cmd_ctx, "stm32x device programming failed");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "stm32x mass erase complete");
+
+ return ERROR_OK;
+}
Code Review / openocd.git / blobdiff