-/* src/flash/s3c2412_nand.c
- *
- * S3C2412 OpenOCD NAND Flash controller support.
- *
- * Copyright 2007,2008 Ben Dooks <ben@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Many thanks to Simtec Electronics for sponsoring this work.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-#include "log.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-#include "nand.h"
-#include "s3c24xx_nand.h"
-#include "target.h"
-
-int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
-int s3c2412_init(struct nand_device_s *device);
-
-nand_flash_controller_t s3c2412_nand_controller =
-{
- .name = "s3c2412",
- .nand_device_command = s3c2412_nand_device_command,
- .register_commands = s3c24xx_register_commands,
- .init = s3c2412_init,
- .reset = s3c24xx_reset,
- .command = s3c24xx_command,
- .address = s3c24xx_address,
- .write_data = s3c24xx_write_data,
- .read_data = s3c24xx_read_data,
- .write_page = s3c24xx_write_page,
- .read_page = s3c24xx_read_page,
- .write_block_data = s3c2440_write_block_data,
- .read_block_data = s3c2440_read_block_data,
- .controller_ready = s3c24xx_controller_ready,
- .nand_ready = s3c2440_nand_ready,
-};
-
-int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
- char **args, int argc,
- struct nand_device_s *device)
-{
- s3c24xx_nand_controller_t *info;
-
- info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
- if (info == NULL) {
- return ERROR_NAND_DEVICE_INVALID;
- }
-
- /* fill in the address fields for the core device */
- info->cmd = S3C2440_NFCMD;
- info->addr = S3C2440_NFADDR;
- info->data = S3C2440_NFDATA;
- info->nfstat = S3C2412_NFSTAT;
-
- return ERROR_OK;
-}
-
-int s3c2412_init(struct nand_device_s *device)
-{
- s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
- target_t *target = s3c24xx_info->target;
- u32 version;
-
- target_write_u32(target, S3C2410_NFCONF,
- S3C2440_NFCONF_TACLS(3) |
- S3C2440_NFCONF_TWRPH0(7) |
- S3C2440_NFCONF_TWRPH1(7));
-
- target_write_u32(target, S3C2440_NFCONT,
- S3C2412_NFCONT_INIT_MAIN_ECC |
- S3C2440_NFCONT_ENABLE);
-
- return ERROR_OK;
-}
+/* src/flash/s3c2412_nand.c\r
+ *\r
+ * S3C2412 OpenOCD NAND Flash controller support.\r
+ *\r
+ * Copyright 2007,2008 Ben Dooks <ben@fluff.org>\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * Many thanks to Simtec Electronics for sponsoring this work.\r
+ */\r
+\r
+#ifdef HAVE_CONFIG_H\r
+#include "config.h"\r
+#endif\r
+\r
+#include "replacements.h"\r
+#include "log.h"\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+#include "nand.h"\r
+#include "s3c24xx_nand.h"\r
+#include "target.h"\r
+\r
+int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);\r
+int s3c2412_init(struct nand_device_s *device);\r
+\r
+nand_flash_controller_t s3c2412_nand_controller =\r
+{\r
+ .name = "s3c2412",\r
+ .nand_device_command = s3c2412_nand_device_command,\r
+ .register_commands = s3c24xx_register_commands,\r
+ .init = s3c2412_init,\r
+ .reset = s3c24xx_reset,\r
+ .command = s3c24xx_command,\r
+ .address = s3c24xx_address,\r
+ .write_data = s3c24xx_write_data,\r
+ .read_data = s3c24xx_read_data,\r
+ .write_page = s3c24xx_write_page,\r
+ .read_page = s3c24xx_read_page,\r
+ .write_block_data = s3c2440_write_block_data,\r
+ .read_block_data = s3c2440_read_block_data,\r
+ .controller_ready = s3c24xx_controller_ready,\r
+ .nand_ready = s3c2440_nand_ready,\r
+};\r
+\r
+int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,\r
+ char **args, int argc,\r
+ struct nand_device_s *device)\r
+{\r
+ s3c24xx_nand_controller_t *info;\r
+\r
+ info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);\r
+ if (info == NULL) {\r
+ return ERROR_NAND_DEVICE_INVALID;\r
+ }\r
+\r
+ /* fill in the address fields for the core device */\r
+ info->cmd = S3C2440_NFCMD;\r
+ info->addr = S3C2440_NFADDR;\r
+ info->data = S3C2440_NFDATA;\r
+ info->nfstat = S3C2412_NFSTAT;\r
+ \r
+ return ERROR_OK;\r
+}\r
+\r
+int s3c2412_init(struct nand_device_s *device)\r
+{\r
+ s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;\r
+ target_t *target = s3c24xx_info->target;\r
+\r
+ target_write_u32(target, S3C2410_NFCONF,\r
+ S3C2440_NFCONF_TACLS(3) |\r
+ S3C2440_NFCONF_TWRPH0(7) |\r
+ S3C2440_NFCONF_TWRPH1(7));\r
+\r
+ target_write_u32(target, S3C2440_NFCONT,\r
+ S3C2412_NFCONT_INIT_MAIN_ECC |\r
+ S3C2440_NFCONT_ENABLE);\r
+\r
+ return ERROR_OK;\r
+}\r