-/***************************************************************************\r
- * Copyright (C) 2005 by Dominic Rath *\r
- * Dominic.Rath@gmx.de *\r
- * *\r
- * Copyright (C) 2008 by Spencer Oliver *\r
- * spen@spen-soft.co.uk *\r
- * *\r
- * Copyright (C) 2008 by John McCarthy *\r
- * jgmcc@magma.ca *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "replacements.h"\r
-\r
-#include "pic32mx.h"\r
-#include "flash.h"\r
-#include "target.h"\r
-#include "log.h"\r
-#include "mips32.h"\r
-#include "algorithm.h"\r
-#include "binarybuffer.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-static\r
-struct pic32mx_devs_s {\r
- u8 devid;\r
- char *name;\r
- u32 pfm_size;\r
-} pic32mx_devs[] = {\r
- { 0x78, "460F512L USB", 512 },\r
- { 0x74, "460F256L USB", 256 },\r
- { 0x6D, "440F128L USB", 128 },\r
- { 0x56, "440F512H USB", 512 },\r
- { 0x52, "440F256H USB", 256 },\r
- { 0x4D, "440F128H USB", 128 },\r
- { 0x42, "420F032H USB", 32 },\r
- { 0x38, "360F512L", 512 },\r
- { 0x34, "360F256L", 256 },\r
- { 0x2D, "340F128L", 128 },\r
- { 0x2A, "320F128L", 128 },\r
- { 0x16, "340F512H", 512 },\r
- { 0x12, "340F256H", 256 },\r
- { 0x0D, "340F128H", 128 },\r
- { 0x0A, "320F128H", 128 },\r
- { 0x06, "320F064H", 64 },\r
- { 0x02, "320F032H", 32 },\r
- { 0x00, NULL, 0 }\r
-};\r
-\r
-int pic32mx_register_commands(struct command_context_s *cmd_ctx);\r
-int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
-int pic32mx_erase(struct flash_bank_s *bank, int first, int last);\r
-int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);\r
-int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
-int pic32mx_probe(struct flash_bank_s *bank);\r
-int pic32mx_auto_probe(struct flash_bank_s *bank);\r
-int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int pic32mx_protect_check(struct flash_bank_s *bank);\r
-int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
-\r
-#if 0\r
-int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-#endif\r
-int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
-int pic32mx_chip_erase(struct flash_bank_s *bank);\r
-\r
-flash_driver_t pic32mx_flash =\r
-{\r
- .name = "pic32mx",\r
- .register_commands = pic32mx_register_commands,\r
- .flash_bank_command = pic32mx_flash_bank_command,\r
- .erase = pic32mx_erase,\r
- .protect = pic32mx_protect,\r
- .write = pic32mx_write,\r
- .probe = pic32mx_probe,\r
- .auto_probe = pic32mx_auto_probe,\r
- .erase_check = default_flash_mem_blank_check,\r
- .protect_check = pic32mx_protect_check,\r
- .info = pic32mx_info\r
-};\r
-\r
-int pic32mx_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- command_t *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx", NULL, COMMAND_ANY, "pic32mx flash specific commands");\r
-\r
-#if 0\r
- register_command(cmd_ctx, pic32mx_cmd, "lock", pic32mx_handle_lock_command, COMMAND_EXEC,\r
- "lock device");\r
- register_command(cmd_ctx, pic32mx_cmd, "unlock", pic32mx_handle_unlock_command, COMMAND_EXEC,\r
- "unlock protected device");\r
-#endif\r
- register_command(cmd_ctx, pic32mx_cmd, "chip_erase", pic32mx_handle_chip_erase_command, COMMAND_EXEC,\r
- "erase device");\r
- register_command(cmd_ctx, pic32mx_cmd, "pgm_word", pic32mx_handle_pgm_word_command, COMMAND_EXEC,\r
- "program a word");\r
- return ERROR_OK;\r
-}\r
-\r
-/* flash bank pic32mx <base> <size> 0 0 <target#>\r
- */\r
-int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
-{\r
- pic32mx_flash_bank_t *pic32mx_info;\r
-\r
- if (argc < 6)\r
- {\r
- LOG_WARNING("incomplete flash_bank pic32mx configuration");\r
- return ERROR_FLASH_BANK_INVALID;\r
- }\r
-\r
- pic32mx_info = malloc(sizeof(pic32mx_flash_bank_t));\r
- bank->driver_priv = pic32mx_info;\r
-\r
- pic32mx_info->write_algorithm = NULL;\r
- pic32mx_info->probed = 0;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-u32 pic32mx_get_flash_status(flash_bank_t *bank)\r
-{\r
- target_t *target = bank->target;\r
- u32 status;\r
-\r
- target_read_u32(target, PIC32MX_NVMCON, &status);\r
-\r
- return status;\r
-}\r
-\r
-u32 pic32mx_wait_status_busy(flash_bank_t *bank, int timeout)\r
-{\r
- u32 status;\r
-\r
- /* wait for busy to clear */\r
- while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))\r
- {\r
- LOG_DEBUG("status: 0x%x", status);\r
- alive_sleep(1);\r
- }\r
- if(timeout <= 0)\r
- LOG_DEBUG("timeout: status: 0x%x", status);\r
-\r
- return status;\r
-}\r
-\r
-int pic32mx_nvm_exec(struct flash_bank_s *bank, u32 op, u32 timeout)\r
-{\r
- target_t *target = bank->target;\r
- u32 status;\r
-\r
- target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN|op);\r
-\r
- /* unlock flash registers */\r
- target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);\r
- target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);\r
-\r
- /* start operation */\r
- target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);\r
-\r
- status = pic32mx_wait_status_busy(bank, timeout);\r
-\r
- /* lock flash registers */\r
- target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);\r
-\r
- return status;\r
-}\r
-\r
-int pic32mx_protect_check(struct flash_bank_s *bank)\r
-{\r
- target_t *target = bank->target;\r
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;\r
-\r
- u32 devcfg0;\r
- int s;\r
- int num_pages;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);\r
- if((devcfg0 & (1<<28)) == 0) /* code protect bit */\r
- num_pages = 0xffff; /* All pages protected */\r
- else if(bank->base == PIC32MX_KSEG1_BOOT_FLASH)\r
- {\r
- if(devcfg0 & (1<<24))\r
- num_pages = 0; /* All pages unprotected */\r
- else\r
- num_pages = 0xffff; /* All pages protected */\r
- }\r
- else /* pgm flash */\r
- num_pages = (~devcfg0 >> 12) & 0xff;\r
- for (s = 0; s < bank->num_sectors && s < num_pages; s++)\r
- bank->sectors[s].is_protected = 1;\r
- for (; s < bank->num_sectors; s++)\r
- bank->sectors[s].is_protected = 0;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_erase(struct flash_bank_s *bank, int first, int last)\r
-{\r
- target_t *target = bank->target;\r
- int i;\r
- u32 status;\r
-\r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
-#if 0\r
- if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))\r
- {\r
- status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);\r
- if( status & NVMCON_NVMERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & NVMCON_LVDERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- return ERROR_OK;\r
- }\r
-#endif\r
-\r
- for (i = first; i <= last; i++)\r
- {\r
- target_write_u32(target, PIC32MX_NVMADDR, bank->base + bank->sectors[i].offset);\r
-\r
- status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);\r
-\r
- if( status & NVMCON_NVMERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & NVMCON_LVDERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- bank->sectors[i].is_erased = 1;\r
- }\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)\r
-{\r
- pic32mx_flash_bank_t *pic32mx_info = NULL;\r
- target_t *target = bank->target;\r
- u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};\r
- int i, reg, bit;\r
- int status;\r
- u32 protection;\r
-\r
- pic32mx_info = bank->driver_priv;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
-#if 0\r
- if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))\r
- {\r
- LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);\r
- return ERROR_FLASH_SECTOR_INVALID;\r
- }\r
-\r
- /* medium density - each bit refers to a 4bank protection\r
- * high density - each bit refers to a 2bank protection */\r
- target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);\r
-\r
- prot_reg[0] = (u16)protection;\r
- prot_reg[1] = (u16)(protection >> 8);\r
- prot_reg[2] = (u16)(protection >> 16);\r
- prot_reg[3] = (u16)(protection >> 24);\r
-\r
- if (pic32mx_info->ppage_size == 2)\r
- {\r
- /* high density flash */\r
-\r
- /* bit 7 controls sector 62 - 255 protection */\r
- if (last > 61)\r
- {\r
- if (set)\r
- prot_reg[3] &= ~(1 << 7);\r
- else\r
- prot_reg[3] |= (1 << 7);\r
- }\r
-\r
- if (first > 61)\r
- first = 62;\r
- if (last > 61)\r
- last = 61;\r
-\r
- for (i = first; i <= last; i++)\r
- {\r
- reg = (i / pic32mx_info->ppage_size) / 8;\r
- bit = (i / pic32mx_info->ppage_size) - (reg * 8);\r
-\r
- if( set )\r
- prot_reg[reg] &= ~(1 << bit);\r
- else\r
- prot_reg[reg] |= (1 << bit);\r
- }\r
- }\r
- else\r
- {\r
- /* medium density flash */\r
- for (i = first; i <= last; i++)\r
- {\r
- reg = (i / pic32mx_info->ppage_size) / 8;\r
- bit = (i / pic32mx_info->ppage_size) - (reg * 8);\r
-\r
- if( set )\r
- prot_reg[reg] &= ~(1 << bit);\r
- else\r
- prot_reg[reg] |= (1 << bit);\r
- }\r
- }\r
-\r
- if ((status = pic32mx_erase_options(bank)) != ERROR_OK)\r
- return status;\r
-\r
- pic32mx_info->option_bytes.protection[0] = prot_reg[0];\r
- pic32mx_info->option_bytes.protection[1] = prot_reg[1];\r
- pic32mx_info->option_bytes.protection[2] = prot_reg[2];\r
- pic32mx_info->option_bytes.protection[3] = prot_reg[3];\r
-\r
- return pic32mx_write_options(bank);\r
-#else\r
- return ERROR_OK;\r
-#endif\r
-}\r
-\r
-int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;\r
- target_t *target = bank->target;\r
- u32 buffer_size = 8192;\r
- working_area_t *source;\r
- u32 address = bank->base + offset;\r
- reg_param_t reg_params[4];\r
-#if 0\r
- armv7m_algorithm_t armv7m_info;\r
- int retval = ERROR_OK;\r
-\r
- u8 pic32mx_flash_write_code[] = {\r
- /* write: */\r
- 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */\r
- 0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */\r
- 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */\r
- 0x23, 0x60, /* str r3, [r4, #0] */\r
- 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */\r
- 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */\r
- /* busy: */\r
- 0x2B, 0x68, /* ldr r3, [r5, #0] */\r
- 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */\r
- 0xFB, 0xD0, /* beq busy */\r
- 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */\r
- 0x01, 0xD1, /* bne exit */\r
- 0x01, 0x3A, /* subs r2, r2, #1 */\r
- 0xED, 0xD1, /* bne write */\r
- /* exit: */\r
- 0xFE, 0xE7, /* b exit */\r
- 0x10, 0x20, 0x02, 0x40, /* PIC32MX_FLASH_CR: .word 0x40022010 */\r
- 0x0C, 0x20, 0x02, 0x40 /* PIC32MX_FLASH_SR: .word 0x4002200C */\r
- };\r
-\r
- /* flash write code */\r
- if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)\r
- {\r
- LOG_WARNING("no working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- };\r
-\r
- if ((retval=target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code))!=ERROR_OK)\r
- return retval;\r
-\r
- /* memory buffer */\r
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)\r
- {\r
- buffer_size /= 2;\r
- if (buffer_size <= 256)\r
- {\r
- /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */\r
- if (pic32mx_info->write_algorithm)\r
- target_free_working_area(target, pic32mx_info->write_algorithm);\r
-\r
- LOG_WARNING("no large enough working area available, can't do block memory writes");\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
- }\r
- };\r
-\r
- armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;\r
- armv7m_info.core_mode = ARMV7M_MODE_ANY;\r
-\r
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT);\r
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);\r
- init_reg_param(®_params[2], "r2", 32, PARAM_OUT);\r
- init_reg_param(®_params[3], "r3", 32, PARAM_IN);\r
-\r
- while (count > 0)\r
- {\r
- u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;\r
-\r
- if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)\r
- break;\r
-\r
- buf_set_u32(reg_params[0].value, 0, 32, source->address);\r
- buf_set_u32(reg_params[1].value, 0, 32, address);\r
- buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);\r
-\r
- if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \\r
- pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)\r
- {\r
- LOG_ERROR("error executing pic32mx flash write algorithm");\r
- retval = ERROR_FLASH_OPERATION_FAILED;\r
- break;\r
- }\r
-\r
- if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)\r
- {\r
- retval = ERROR_FLASH_OPERATION_FAILED;\r
- break;\r
- }\r
-\r
- buffer += thisrun_count * 2;\r
- address += thisrun_count * 2;\r
- count -= thisrun_count;\r
- }\r
-\r
- target_free_working_area(target, source);\r
- target_free_working_area(target, pic32mx_info->write_algorithm);\r
-\r
- destroy_reg_param(®_params[0]);\r
- destroy_reg_param(®_params[1]);\r
- destroy_reg_param(®_params[2]);\r
- destroy_reg_param(®_params[3]);\r
-\r
- return retval;\r
-#else\r
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;\r
-#endif\r
-}\r
-\r
-int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)\r
-{\r
- target_t *target = bank->target;\r
-\r
- target_write_u32(target, PIC32MX_NVMADDR, address);\r
- target_write_u32(target, PIC32MX_NVMDATA, word);\r
-\r
- return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);\r
-}\r
-\r
-int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
-{\r
- target_t *target = bank->target;\r
- u32 words_remaining = (count / 4);\r
- u32 bytes_remaining = (count & 0x00000003);\r
- u32 address = bank->base + offset;\r
- u32 bytes_written = 0;\r
- u32 status;\r
- u32 retval;\r
-\r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- if (offset & 0x3)\r
- {\r
- LOG_WARNING("offset 0x%x breaks required 4-byte alignment", offset);\r
- return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
- }\r
-\r
- /* multiple words (4-byte) to be programmed? */\r
- if (words_remaining > 0)\r
- {\r
- /* try using a block write */\r
- if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)\r
- {\r
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)\r
- {\r
- /* if block write failed (no sufficient working area),\r
- * we use normal (slow) single dword accesses */\r
- LOG_WARNING("couldn't use block writes, falling back to single memory accesses");\r
- }\r
- else if (retval == ERROR_FLASH_OPERATION_FAILED)\r
- {\r
- LOG_ERROR("flash writing failed with error code: 0x%x", retval);\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- }\r
- else\r
- {\r
- buffer += words_remaining * 4;\r
- address += words_remaining * 4;\r
- words_remaining = 0;\r
- }\r
- }\r
-\r
- while (words_remaining > 0)\r
- {\r
- status = pic32mx_write_word(bank, address, *(u32*)(buffer + bytes_written));\r
-\r
- if( status & NVMCON_NVMERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & NVMCON_LVDERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
-\r
- bytes_written += 4;\r
- words_remaining--;\r
- address += 4;\r
- }\r
-\r
- if (bytes_remaining)\r
- {\r
- u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};\r
- int i = 0;\r
-\r
- while(bytes_remaining > 0)\r
- {\r
- /* Assumes little endian */\r
- last_word[i++] = *(buffer + bytes_written);\r
- bytes_remaining--;\r
- bytes_written++;\r
- }\r
-\r
- status = pic32mx_write_word(bank, address, *(u32*)last_word);\r
-\r
- if( status & NVMCON_NVMERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- if( status & NVMCON_LVDERR )\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_probe(struct flash_bank_s *bank)\r
-{\r
- target_t *target = bank->target;\r
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;\r
- mips32_common_t *mips32 = target->arch_info;\r
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;\r
- int i;\r
- u16 num_pages;\r
- u32 device_id;\r
- int page_size;\r
-\r
- pic32mx_info->probed = 0;\r
-\r
- device_id = ejtag_info->idcode;\r
- LOG_INFO( "device id = 0x%08x (manuf 0x%03x dev 0x%02x, ver 0x%03x)", device_id, (device_id>>1)&0x7ff, (device_id>>12)&0xff, (device_id>>20)&0xfff );\r
-\r
- if(((device_id>>1)&0x7ff) != PIC32MX_MANUF_ID) {\r
- LOG_WARNING( "Cannot identify target as a PIC32MX family." );\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
-\r
- page_size = 4096;\r
- if(bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {\r
- /* 0xBFC00000: Boot flash size fixed at 12k */\r
- num_pages = 12;\r
- } else {\r
- /* 0xBD000000: Program flash size varies with device */\r
- for(i=0; pic32mx_devs[i].name != NULL; i++)\r
- if(pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {\r
- num_pages = pic32mx_devs[i].pfm_size;\r
- break;\r
- }\r
- if(pic32mx_devs[i].name == NULL) {\r
- LOG_WARNING( "Cannot identify target as a PIC32MX family." );\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- }\r
-\r
-#if 0\r
- if (bank->target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- /* get flash size from target */\r
- if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)\r
- {\r
- /* failed reading flash size, default to max target family */\r
- num_pages = 0xffff;\r
- }\r
-#endif\r
-\r
- LOG_INFO( "flash size = %dkbytes", num_pages );\r
-\r
- /* calculate numbers of pages */\r
- num_pages /= (page_size / 1024);\r
-\r
- if(bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;\r
- if(bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;\r
- bank->size = (num_pages * page_size);\r
- bank->num_sectors = num_pages;\r
- bank->chip_width = 4;\r
- bank->bus_width = 4;\r
- bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);\r
-\r
- for (i = 0; i < num_pages; i++)\r
- {\r
- bank->sectors[i].offset = i * page_size;\r
- bank->sectors[i].size = page_size;\r
- bank->sectors[i].is_erased = -1;\r
- bank->sectors[i].is_protected = 1;\r
- }\r
-\r
- pic32mx_info->probed = 1;\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_auto_probe(struct flash_bank_s *bank)\r
-{\r
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;\r
- if (pic32mx_info->probed)\r
- return ERROR_OK;\r
- return pic32mx_probe(bank);\r
-}\r
-\r
-int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
-{\r
- target_t *target = bank->target;\r
- mips32_common_t *mips32 = target->arch_info;\r
- mips_ejtag_t *ejtag_info = &mips32->ejtag_info;\r
- u32 device_id;\r
- int printed, i;\r
-\r
- device_id = ejtag_info->idcode;\r
-\r
- if(((device_id>>1)&0x7ff) != PIC32MX_MANUF_ID) {\r
- snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n", (device_id>>1)&0x7ff, PIC32MX_MANUF_ID);\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- for(i=0; pic32mx_devs[i].name != NULL; i++)\r
- if(pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {\r
- printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);\r
- break;\r
- }\r
- if(pic32mx_devs[i].name == NULL) {\r
- snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");\r
- return ERROR_FLASH_OPERATION_FAILED;\r
- }\r
- buf += printed;\r
- buf_size -= printed;\r
- printed = snprintf(buf, buf_size, " Ver: 0x%03x", (device_id>>20)&0xfff);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-#if 0\r
-int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- pic32mx_flash_bank_t *pic32mx_info = NULL;\r
-\r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "pic32mx lock <bank>");\r
- return ERROR_OK;\r
- }\r
-\r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
-\r
- pic32mx_info = bank->driver_priv;\r
-\r
- target = bank->target;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- if (pic32mx_erase_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "pic32mx failed to erase options");\r
- return ERROR_OK;\r
- }\r
-\r
- /* set readout protection */\r
- pic32mx_info->option_bytes.RDP = 0;\r
-\r
- if (pic32mx_write_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "pic32mx failed to lock device");\r
- return ERROR_OK;\r
- }\r
-\r
- command_print(cmd_ctx, "pic32mx locked");\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- target_t *target = NULL;\r
- pic32mx_flash_bank_t *pic32mx_info = NULL;\r
-\r
- if (argc < 1)\r
- {\r
- command_print(cmd_ctx, "pic32mx unlock <bank>");\r
- return ERROR_OK;\r
- }\r
-\r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
-\r
- pic32mx_info = bank->driver_priv;\r
-\r
- target = bank->target;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- if (pic32mx_erase_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "pic32mx failed to unlock device");\r
- return ERROR_OK;\r
- }\r
-\r
- if (pic32mx_write_options(bank) != ERROR_OK)\r
- {\r
- command_print(cmd_ctx, "pic32mx failed to lock device");\r
- return ERROR_OK;\r
- }\r
-\r
- command_print(cmd_ctx, "pic32mx unlocked");\r
-\r
- return ERROR_OK;\r
-}\r
-#endif\r
-\r
-int pic32mx_chip_erase(struct flash_bank_s *bank)\r
-{\r
- target_t *target = bank->target;\r
- u32 status;\r
-\r
- if (target->state != TARGET_HALTED)\r
- {\r
- LOG_ERROR("Target not halted");\r
- return ERROR_TARGET_NOT_HALTED;\r
- }\r
-\r
- LOG_INFO("PIC32MX chip erase called");\r
-\r
-#if 0\r
- /* unlock option flash registers */\r
- target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);\r
- target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);\r
-\r
- /* chip erase flash memory */\r
- target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);\r
- target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER|FLASH_STRT);\r
-\r
- status = pic32mx_wait_status_busy(bank, 10);\r
-\r
- target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);\r
-\r
- if( status & FLASH_WRPRTERR )\r
- {\r
- LOG_ERROR("pic32mx device protected");\r
- return ERROR_OK;\r
- }\r
-\r
- if( status & FLASH_PGERR )\r
- {\r
- LOG_ERROR("pic32mx device programming failed");\r
- return ERROR_OK;\r
- }\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- int i;\r
-\r
-#if 0\r
- if (argc != 0)\r
- {\r
- command_print(cmd_ctx, "pic32mx chip_erase");\r
- return ERROR_OK;\r
- }\r
-\r
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
-\r
- if (pic32mx_chip_erase(bank) == ERROR_OK)\r
- {\r
- /* set all sectors as erased */\r
- for (i = 0; i < bank->num_sectors; i++)\r
- {\r
- bank->sectors[i].is_erased = 1;\r
- }\r
-\r
- command_print(cmd_ctx, "pic32mx chip erase complete");\r
- }\r
- else\r
- {\r
- command_print(cmd_ctx, "pic32mx chip erase failed");\r
- }\r
-#endif\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
-{\r
- flash_bank_t *bank;\r
- u32 address, value;\r
- int i;\r
- int status, res;\r
-\r
- if (argc != 3)\r
- {\r
- command_print(cmd_ctx, "pic32mx pgm_word <addr> <value> <bank>");\r
- return ERROR_OK;\r
- }\r
-\r
- address = strtoul(args[0], NULL, 0);\r
- value = strtoul(args[1], NULL, 0);\r
-\r
- bank = get_flash_bank_by_num(strtoul(args[2], NULL, 0));\r
- if (!bank)\r
- {\r
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[2]);\r
- return ERROR_OK;\r
- }\r
- if (address < bank->base || address >= (bank->base+bank->size))\r
- {\r
- command_print(cmd_ctx, "flash address '%s' is out of bounds", args[0]);\r
- return ERROR_OK;\r
- }\r
-\r
- res = ERROR_OK;\r
- status = pic32mx_write_word(bank, address, value);\r
- if( status & NVMCON_NVMERR )\r
- res = ERROR_FLASH_OPERATION_FAILED;\r
- if( status & NVMCON_LVDERR )\r
- res = ERROR_FLASH_OPERATION_FAILED;\r
-\r
- if (res == ERROR_OK)\r
- command_print(cmd_ctx, "pic32mx pgm word complete");\r
- else\r
- command_print(cmd_ctx, "pic32mx pgm word failed (status=0x%x)", status);\r
-\r
- return ERROR_OK;\r
-}\r
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2008 by John McCarthy *
+ * jgmcc@magma.ca *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "pic32mx.h"
+#include "mips32.h"
+
+
+static
+struct pic32mx_devs_s {
+ uint8_t devid;
+ char *name;
+ uint32_t pfm_size;
+} pic32mx_devs[] = {
+ { 0x78, "460F512L USB", 512 },
+ { 0x74, "460F256L USB", 256 },
+ { 0x6D, "440F128L USB", 128 },
+ { 0x56, "440F512H USB", 512 },
+ { 0x52, "440F256H USB", 256 },
+ { 0x4D, "440F128H USB", 128 },
+ { 0x42, "420F032H USB", 32 },
+ { 0x38, "360F512L", 512 },
+ { 0x34, "360F256L", 256 },
+ { 0x2D, "340F128L", 128 },
+ { 0x2A, "320F128L", 128 },
+ { 0x16, "340F512H", 512 },
+ { 0x12, "340F256H", 256 },
+ { 0x0D, "340F128H", 128 },
+ { 0x0A, "320F128H", 128 },
+ { 0x06, "320F064H", 64 },
+ { 0x02, "320F032H", 32 },
+ { 0x00, NULL, 0 }
+};
+
+static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr);
+static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word);
+
+/* flash bank pic32mx <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
+{
+ struct pic32mx_flash_bank *pic32mx_info;
+
+ if (CMD_ARGC < 6)
+ {
+ LOG_WARNING("incomplete flash_bank pic32mx configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
+ bank->driver_priv = pic32mx_info;
+
+ pic32mx_info->write_algorithm = NULL;
+ pic32mx_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static uint32_t pic32mx_get_flash_status(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ uint32_t status;
+
+ target_read_u32(target, PIC32MX_NVMCON, &status);
+
+ return status;
+}
+
+static uint32_t pic32mx_wait_status_busy(struct flash_bank *bank, int timeout)
+{
+ uint32_t status;
+
+ /* wait for busy to clear */
+ while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
+ {
+ LOG_DEBUG("status: 0x%" PRIx32, status);
+ alive_sleep(1);
+ }
+ if (timeout <= 0)
+ LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
+
+ return status;
+}
+
+static int pic32mx_nvm_exec(struct flash_bank *bank, uint32_t op, uint32_t timeout)
+{
+ struct target *target = bank->target;
+ uint32_t status;
+
+ target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
+
+ /* unlock flash registers */
+ target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
+ target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);
+
+ /* start operation */
+ target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);
+
+ status = pic32mx_wait_status_busy(bank, timeout);
+
+ /* lock flash registers */
+ target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);
+
+ return status;
+}
+
+static int pic32mx_protect_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+
+ uint32_t devcfg0;
+ int s;
+ int num_pages;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
+ if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
+ num_pages = 0xffff; /* All pages protected */
+ else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
+ {
+ if (devcfg0 & (1 << 24))
+ num_pages = 0; /* All pages unprotected */
+ else
+ num_pages = 0xffff; /* All pages protected */
+ }
+ else /* pgm flash */
+ num_pages = (~devcfg0 >> 12) & 0xff;
+ for (s = 0; s < bank->num_sectors && s < num_pages; s++)
+ bank->sectors[s].is_protected = 1;
+ for (; s < bank->num_sectors; s++)
+ bank->sectors[s].is_protected = 0;
+
+ return ERROR_OK;
+}
+
+static int pic32mx_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ int i;
+ uint32_t status;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
+ {
+ LOG_DEBUG("Erasing entire program flash");
+ status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
+ if (status & NVMCON_NVMERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ if (status & NVMCON_LVDERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ return ERROR_OK;
+ }
+
+ for (i = first; i <= last; i++)
+ {
+ if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(bank->base + bank->sectors[i].offset));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(bank->base + bank->sectors[i].offset));
+
+ status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
+
+ if (status & NVMCON_NVMERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ if (status & NVMCON_LVDERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ bank->sectors[i].is_erased = 1;
+ }
+
+ return ERROR_OK;
+}
+
+static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct pic32mx_flash_bank *pic32mx_info = NULL;
+ struct target *target = bank->target;
+#if 0
+ uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+ int i, reg, bit;
+ int status;
+ uint32_t protection;
+#endif
+
+ pic32mx_info = bank->driver_priv;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+#if 0
+ if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))
+ {
+ LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ /* medium density - each bit refers to a 4bank protection
+ * high density - each bit refers to a 2bank protection */
+ target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
+
+ prot_reg[0] = (uint16_t)protection;
+ prot_reg[1] = (uint16_t)(protection >> 8);
+ prot_reg[2] = (uint16_t)(protection >> 16);
+ prot_reg[3] = (uint16_t)(protection >> 24);
+
+ if (pic32mx_info->ppage_size == 2)
+ {
+ /* high density flash */
+
+ /* bit 7 controls sector 62 - 255 protection */
+ if (last > 61)
+ {
+ if (set)
+ prot_reg[3] &= ~(1 << 7);
+ else
+ prot_reg[3] |= (1 << 7);
+ }
+
+ if (first > 61)
+ first = 62;
+ if (last > 61)
+ last = 61;
+
+ for (i = first; i <= last; i++)
+ {
+ reg = (i / pic32mx_info->ppage_size) / 8;
+ bit = (i / pic32mx_info->ppage_size) - (reg * 8);
+
+ if (set)
+ prot_reg[reg] &= ~(1 << bit);
+ else
+ prot_reg[reg] |= (1 << bit);
+ }
+ }
+ else
+ {
+ /* medium density flash */
+ for (i = first; i <= last; i++)
+ {
+ reg = (i / pic32mx_info->ppage_size) / 8;
+ bit = (i / pic32mx_info->ppage_size) - (reg * 8);
+
+ if (set)
+ prot_reg[reg] &= ~(1 << bit);
+ else
+ prot_reg[reg] |= (1 << bit);
+ }
+ }
+
+ if ((status = pic32mx_erase_options(bank)) != ERROR_OK)
+ return status;
+
+ pic32mx_info->option_bytes.protection[0] = prot_reg[0];
+ pic32mx_info->option_bytes.protection[1] = prot_reg[1];
+ pic32mx_info->option_bytes.protection[2] = prot_reg[2];
+ pic32mx_info->option_bytes.protection[3] = prot_reg[3];
+
+ return pic32mx_write_options(bank);
+#else
+ return ERROR_OK;
+#endif
+}
+
+static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 512;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ int retval = ERROR_OK;
+#if 0
+ struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
+ struct armv7m_algorithm armv7m_info;
+
+ uint8_t pic32mx_flash_write_code[] = {
+ /* write: */
+ 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */
+ 0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */
+ 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
+ 0x23, 0x60, /* str r3, [r4, #0] */
+ 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
+ 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
+ /* busy: */
+ 0x2B, 0x68, /* ldr r3, [r5, #0] */
+ 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
+ 0xFB, 0xD0, /* beq busy */
+ 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
+ 0x01, 0xD1, /* bne exit */
+ 0x01, 0x3A, /* subs r2, r2, #1 */
+ 0xED, 0xD1, /* bne write */
+ /* exit: */
+ 0xFE, 0xE7, /* b exit */
+ 0x10, 0x20, 0x02, 0x40, /* PIC32MX_FLASH_CR: .word 0x40022010 */
+ 0x0C, 0x20, 0x02, 0x40 /* PIC32MX_FLASH_SR: .word 0x4002200C */
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)
+ {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ };
+
+ if ((retval = target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code)) != ERROR_OK)
+ return retval;
+#endif
+
+ /* memory buffer */
+ if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ {
+#if 0
+ /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+ if (pic32mx_info->write_algorithm)
+ target_free_working_area(target, pic32mx_info->write_algorithm);
+#endif
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ while (count >= buffer_size/4)
+ {
+ uint32_t status;
+
+ if ((retval = target_write_buffer(target, source->address, buffer_size, buffer)) != ERROR_OK) {
+ LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
+ break;
+ }
+
+#if 0
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, buffer_size/4);
+
+ if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
+ pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
+ {
+ LOG_ERROR("error executing pic32mx flash write algorithm");
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
+ {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+#endif
+ status = pic32mx_write_row(bank, address, source->address);
+ if (status & NVMCON_NVMERR) {
+ LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+ if (status & NVMCON_LVDERR) {
+ LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += buffer_size;
+ address += buffer_size;
+ count -= buffer_size/4;
+ }
+
+ target_free_working_area(target, source);
+
+ while (count > 0)
+ {
+ uint32_t value;
+ memcpy(&value, buffer, sizeof(uint32_t));
+
+ uint32_t status = pic32mx_write_word(bank, address, value);
+ if (status & NVMCON_NVMERR) {
+ LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+ if (status & NVMCON_LVDERR) {
+ LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += 4;
+ address += 4;
+ count--;
+ }
+
+ return retval;
+}
+
+static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word)
+{
+ struct target *target = bank->target;
+
+ if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
+ target_write_u32(target, PIC32MX_NVMDATA, word);
+
+ return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
+}
+
+/*
+ * Write a 128 word (512 byte) row to flash address from RAM srcaddr.
+ */
+static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr)
+{
+ struct target *target = bank->target;
+
+ LOG_DEBUG("addr: 0x%08" PRIx32 " srcaddr: 0x%08" PRIx32 "", address, srcaddr);
+
+ if (address >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
+ if (srcaddr >= PIC32MX_KSEG1_RAM)
+ target_write_u32(target, PIC32MX_NVMSRCADDR, KS1Virt2Phys(srcaddr));
+ else
+ target_write_u32(target, PIC32MX_NVMSRCADDR, KS0Virt2Phys(srcaddr));
+
+ return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
+}
+
+static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ uint32_t words_remaining = (count / 4);
+ uint32_t bytes_remaining = (count & 0x00000003);
+ uint32_t address = bank->base + offset;
+ uint32_t bytes_written = 0;
+ uint32_t status;
+ int retval;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x3)
+ {
+ LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ /* multiple words (4-byte) to be programmed? */
+ if (words_remaining > 0)
+ {
+ /* try using a block write */
+ if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
+ {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+ {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single dword accesses */
+ LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+ }
+ else if (retval == ERROR_FLASH_OPERATION_FAILED)
+ {
+ LOG_ERROR("flash writing failed with error code: 0x%x", retval);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ }
+ else
+ {
+ buffer += words_remaining * 4;
+ address += words_remaining * 4;
+ words_remaining = 0;
+ }
+ }
+
+ while (words_remaining > 0)
+ {
+ uint32_t value;
+ memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
+
+ status = pic32mx_write_word(bank, address, value);
+ if (status & NVMCON_NVMERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ if (status & NVMCON_LVDERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ bytes_written += 4;
+ words_remaining--;
+ address += 4;
+ }
+
+ if (bytes_remaining)
+ {
+ uint32_t value = 0xffffffff;
+ memcpy(&value, buffer + bytes_written, bytes_remaining);
+
+ status = pic32mx_write_word(bank, address, value);
+ if (status & NVMCON_NVMERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ if (status & NVMCON_LVDERR)
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+static int pic32mx_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ int i;
+ uint16_t num_pages = 0;
+ uint32_t device_id;
+ int page_size;
+
+ pic32mx_info->probed = 0;
+
+ device_id = ejtag_info->idcode;
+ LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
+ device_id,
+ (unsigned)((device_id >> 1)&0x7ff),
+ (unsigned)((device_id >> 12)&0xff),
+ (unsigned)((device_id >> 20)&0xfff));
+
+ if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
+ LOG_WARNING("Cannot identify target as a PIC32MX family.");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ page_size = 4096;
+ if (bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {
+ /* 0xBFC00000: Boot flash size fixed at 12k */
+ num_pages = 12;
+ } else {
+ /* 0xBD000000: Program flash size varies with device */
+ for (i = 0; pic32mx_devs[i].name != NULL; i++)
+ if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
+ num_pages = pic32mx_devs[i].pfm_size;
+ break;
+ }
+ if (pic32mx_devs[i].name == NULL) {
+ LOG_WARNING("Cannot identify target as a PIC32MX family.");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ }
+
+#if 0
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* get flash size from target */
+ if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
+ {
+ /* failed reading flash size, default to max target family */
+ num_pages = 0xffff;
+ }
+#endif
+
+ LOG_INFO("flash size = %dkbytes", num_pages);
+
+ /* calculate numbers of pages */
+ num_pages /= (page_size / 1024);
+
+ if (bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;
+ if (bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;
+ bank->size = (num_pages * page_size);
+ bank->num_sectors = num_pages;
+ bank->chip_width = 4;
+ bank->bus_width = 4;
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+
+ for (i = 0; i < num_pages; i++)
+ {
+ bank->sectors[i].offset = i * page_size;
+ bank->sectors[i].size = page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ pic32mx_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int pic32mx_auto_probe(struct flash_bank *bank)
+{
+ struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
+ if (pic32mx_info->probed)
+ return ERROR_OK;
+ return pic32mx_probe(bank);
+}
+
+#if 0
+COMMAND_HANDLER(pic32mx_handle_part_id_command)
+{
+ return ERROR_OK;
+}
+#endif
+
+static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct target *target = bank->target;
+ struct mips32_common *mips32 = target->arch_info;
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ uint32_t device_id;
+ int printed = 0, i;
+
+ device_id = ejtag_info->idcode;
+
+ if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
+ snprintf(buf, buf_size,
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
+ (unsigned)((device_id >> 1)&0x7ff),
+ PIC32MX_MANUF_ID);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ for (i = 0; pic32mx_devs[i].name != NULL; i++)
+ if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
+ printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
+ break;
+ }
+ if (pic32mx_devs[i].name == NULL) {
+ snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ buf += printed;
+ buf_size -= printed;
+ printed = snprintf(buf, buf_size, " Ver: 0x%03x",
+ (unsigned)((device_id >> 20)&0xfff));
+
+ return ERROR_OK;
+}
+
+#if 0
+COMMAND_HANDLER(pic32mx_handle_lock_command)
+{
+ struct target *target = NULL;
+ struct pic32mx_flash_bank *pic32mx_info = NULL;
+
+ if (CMD_ARGC < 1)
+ {
+ command_print(cmd_ctx, "pic32mx lock <bank>");
+ return ERROR_OK;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ pic32mx_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (pic32mx_erase_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "pic32mx failed to erase options");
+ return ERROR_OK;
+ }
+
+ /* set readout protection */
+ pic32mx_info->option_bytes.RDP = 0;
+
+ if (pic32mx_write_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "pic32mx failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "pic32mx locked");
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(pic32mx_handle_unlock_command)
+{
+ struct target *target = NULL;
+ struct pic32mx_flash_bank *pic32mx_info = NULL;
+
+ if (CMD_ARGC < 1)
+ {
+ command_print(cmd_ctx, "pic32mx unlock <bank>");
+ return ERROR_OK;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ pic32mx_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (pic32mx_erase_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "pic32mx failed to unlock device");
+ return ERROR_OK;
+ }
+
+ if (pic32mx_write_options(bank) != ERROR_OK)
+ {
+ command_print(cmd_ctx, "pic32mx failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(cmd_ctx, "pic32mx unlocked");
+
+ return ERROR_OK;
+}
+#endif
+
+#if 0
+static int pic32mx_chip_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+#if 0
+ uint32_t status;
+#endif
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_INFO("PIC32MX chip erase called");
+
+#if 0
+ /* unlock option flash registers */
+ target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);
+ target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);
+
+ /* chip erase flash memory */
+ target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
+ target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER | FLASH_STRT);
+
+ status = pic32mx_wait_status_busy(bank, 10);
+
+ target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);
+
+ if (status & FLASH_WRPRTERR)
+ {
+ LOG_ERROR("pic32mx device protected");
+ return ERROR_OK;
+ }
+
+ if (status & FLASH_PGERR)
+ {
+ LOG_ERROR("pic32mx device programming failed");
+ return ERROR_OK;
+ }
+#endif
+
+ return ERROR_OK;
+}
+#endif
+
+COMMAND_HANDLER(pic32mx_handle_chip_erase_command)
+{
+#if 0
+ int i;
+
+ if (CMD_ARGC != 0)
+ {
+ command_print(cmd_ctx, "pic32mx chip_erase");
+ return ERROR_OK;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ if (pic32mx_chip_erase(bank) == ERROR_OK)
+ {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ bank->sectors[i].is_erased = 1;
+ }
+
+ command_print(cmd_ctx, "pic32mx chip erase complete");
+ }
+ else
+ {
+ command_print(cmd_ctx, "pic32mx chip erase failed");
+ }
+#endif
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
+{
+ uint32_t address, value;
+ int status, res;
+
+ if (CMD_ARGC != 3)
+ {
+ command_print(cmd_ctx, "pic32mx pgm_word <addr> <value> <bank>");
+ return ERROR_OK;
+ }
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank_by_num, 2, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ if (address < bank->base || address >= (bank->base + bank->size))
+ {
+ command_print(cmd_ctx, "flash address '%s' is out of bounds", CMD_ARGV[0]);
+ return ERROR_OK;
+ }
+
+ res = ERROR_OK;
+ status = pic32mx_write_word(bank, address, value);
+ if (status & NVMCON_NVMERR)
+ res = ERROR_FLASH_OPERATION_FAILED;
+ if (status & NVMCON_LVDERR)
+ res = ERROR_FLASH_OPERATION_FAILED;
+
+ if (res == ERROR_OK)
+ command_print(cmd_ctx, "pic32mx pgm word complete");
+ else
+ command_print(cmd_ctx, "pic32mx pgm word failed (status = 0x%x)", status);
+
+ return ERROR_OK;
+}
+
+static int pic32mx_register_commands(struct command_context *cmd_ctx)
+{
+ struct command *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx",
+ NULL, COMMAND_ANY, "pic32mx flash specific commands");
+#if 0
+ register_command(cmd_ctx, pic32mx_cmd, "lock",
+ pic32mx_handle_lock_command, COMMAND_EXEC,
+ "lock device");
+ register_command(cmd_ctx, pic32mx_cmd, "unlock",
+ pic32mx_handle_unlock_command, COMMAND_EXEC,
+ "unlock protected device");
+#endif
+ register_command(cmd_ctx, pic32mx_cmd, "chip_erase",
+ pic32mx_handle_chip_erase_command, COMMAND_EXEC,
+ "erase device");
+ register_command(cmd_ctx, pic32mx_cmd, "pgm_word",
+ pic32mx_handle_pgm_word_command, COMMAND_EXEC,
+ "program a word");
+ return ERROR_OK;
+}
+
+struct flash_driver pic32mx_flash = {
+ .name = "pic32mx",
+ .register_commands = &pic32mx_register_commands,
+ .flash_bank_command = &pic32mx_flash_bank_command,
+ .erase = &pic32mx_erase,
+ .protect = &pic32mx_protect,
+ .write = &pic32mx_write,
+ .probe = &pic32mx_probe,
+ .auto_probe = &pic32mx_auto_probe,
+ .erase_check = &default_flash_mem_blank_check,
+ .protect_check = &pic32mx_protect_check,
+ .info = &pic32mx_info,
+ };
Code Review / openocd.git / blobdiff