target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
- status = stm32x_wait_status_busy(bank, 10);
+ status = stm32x_wait_status_busy(bank, 100);
if (status & FLASH_WRPRTERR)
return ERROR_FLASH_OPERATION_FAILED;
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
+ /* see contib/loaders/flash/stm32x.s for src */
+
static const uint8_t stm32x_flash_write_code[] = {
/* write: */
0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
0x01, 0xD1, /* bne exit */
0x01, 0x3A, /* subs r2, r2, #1 */
0xED, 0xD1, /* bne write */
+ /* exit: */
0x00, 0xBE, /* bkpt #0 */
0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
return retval;
/* memory buffer */
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
{
buffer_size /= 2;
if (buffer_size <= 256)
if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
stm32x_info->write_algorithm->address,
- stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10),
+ 0,
10000, &armv7m_info)) != ERROR_OK)
{
LOG_ERROR("error executing stm32x flash write algorithm");
uint32_t device_id;
int page_size;
- if (bank->target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
stm32x_info->probed = 0;
/* read stm32 device id register */
/* calculate numbers of pages */
num_pages /= (page_size / 1024);
+ if (bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
bank->base = 0x08000000;
bank->size = (num_pages * page_size);
bank->num_sectors = num_pages;
}
#endif
-static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
{
struct target *target = bank->target;
uint32_t device_id;
target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
- status = stm32x_wait_status_busy(bank, 10);
+ status = stm32x_wait_status_busy(bank, 100);
target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
if (status & FLASH_WRPRTERR)
{
LOG_ERROR("stm32x device protected");
- return ERROR_OK;
+ return ERROR_FLASH_OPERATION_FAILED;
}
if (status & FLASH_PGERR)
{
LOG_ERROR("stm32x device programming failed");
- return ERROR_OK;
+ return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
if (ERROR_OK != retval)
return retval;
- if (stm32x_mass_erase(bank) == ERROR_OK)
+ retval = stm32x_mass_erase(bank);
+ if (retval == ERROR_OK)
{
/* set all sectors as erased */
for (i = 0; i < bank->num_sectors; i++)
command_print(CMD_CTX, "stm32x mass erase failed");
}
- return ERROR_OK;
+ return retval;
}
static const struct command_registration stm32x_exec_command_handlers[] = {
.erase = stm32x_erase,
.protect = stm32x_protect,
.write = stm32x_write,
+ .read = default_flash_read,
.probe = stm32x_probe,
.auto_probe = stm32x_auto_probe,
.erase_check = default_flash_mem_blank_check,
.protect_check = stm32x_protect_check,
- .info = stm32x_info,
+ .info = get_stm32x_info,
};