* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
* To reduce testing complexity and dangers of regressions,
* a seperate file is used for stm32fx2x.
*
- * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
+ * Sector sizes in kiBytes:
+ * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
+ * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
+ * 1 MiByte STM32F42x/43x part with DB1M Option set:
+ * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
*
- * What's the protection page size???
+ * STM32F7
+ * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
+ *
+ * Protection size is sector size.
*
* Tested with STM3220F-EVAL board.
*
- * STM32F21xx series for reference.
+ * STM32F4xx series for reference.
*
- * RM0033
- * http://www.st.com/internet/mcu/product/250192.jsp
+ * RM0090
+ * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
*
* PM0059
* www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
* PROGRAMMING_MANUAL/CD00233952.pdf
*
+ * STM32F7xx series for reference.
+ *
+ * RM0385
+ * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
+ *
* STM32F1x series - notice that this code was copy, pasted and knocked
* into a stm32f2x driver, so in case something has been converted or
* bugs haven't been fixed, here are the original manuals:
#define FLASH_PSIZE_16 (1 << 8)
#define FLASH_PSIZE_32 (2 << 8)
#define FLASH_PSIZE_64 (3 << 8)
-#define FLASH_SNB(a) ((a) << 3)
+/* The sector number encoding is not straight binary for dual bank flash.
+ * Warning: evaluates the argument multiple times */
+#define FLASH_SNB(a) ((((a) >= 12) ? 0x10 | ((a) - 12) : (a)) << 3)
#define FLASH_LOCK (1 << 31)
/* FLASH_SR register bits */
#define OPT_RDRSTSTOP 3
#define OPT_RDRSTSTDBY 4
#define OPT_BFB2 5 /* dual flash bank only */
+#define OPT_DB1M 14 /* 1 MiB devices dual flash bank option */
/* register unlock keys */
return retval;
if (ctrl & FLASH_LOCK) {
- LOG_ERROR("flash not unlocked STM32_FLASH_CR: %x", ctrl);
+ LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
return retval;
if (ctrl & OPT_LOCK) {
- LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %x", ctrl);
+ LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
/* rebuild option data */
optiondata = stm32x_info->option_bytes.user_options;
- buf_set_u32(&optiondata, 8, 8, stm32x_info->option_bytes.RDP);
- buf_set_u32(&optiondata, 16, 12, stm32x_info->option_bytes.protection);
+ optiondata |= stm32x_info->option_bytes.RDP << 8;
+ optiondata |= (stm32x_info->option_bytes.protection & 0x0fff) << 16;
/* program options */
retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
if (stm32x_info->has_large_mem) {
uint32_t optiondata2 = 0;
- buf_set_u32(&optiondata2, 16, 12, stm32x_info->option_bytes.protection >> 12);
+ optiondata2 |= (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
if (retval != ERROR_OK)
return retval;
return retval;
/* relock registers */
- retval = target_write_u32(target, STM32_FLASH_OPTCR, OPT_LOCK);
+ retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPT_LOCK);
if (retval != ERROR_OK)
return retval;
static int stm32x_protect_check(struct flash_bank *bank)
{
- struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
/* read write protection settings */
int retval = stm32x_read_options(bank);
if (retval != ERROR_OK) {
struct target *target = bank->target;
int i;
+ assert(first < bank->num_sectors);
+ assert(last < bank->num_sectors);
+
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
To erase a sector, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
- 2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block)
+ 2. Set the SER bit and select the sector
you wish to erase (SNB) in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be cleared
return ERROR_OK;
}
-static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
0x47, 0x45, /* cmp r7, r8 */
0xF7, 0xD0, /* beq wait_fifo */
- 0xDF, 0xF8, 0x30, 0x60, /* ldr r6, STM32_PROG16 */
+ 0xDF, 0xF8, 0x34, 0x60, /* ldr r6, STM32_PROG16 */
0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */
0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */
+ 0xBF, 0xF3, 0x4F, 0x8F, /* dsb sy */
/* busy: */
0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */
0x47, 0x60, /* str r7, [r0, #4] */
0x01, 0x3B, /* subs r3, r3, #1 */
0x13, 0xB1, /* cbz r3, exit */
- 0xE1, 0xE7, /* b wait_fifo */
+ 0xDF, 0xE7, /* b wait_fifo */
/* error: */
0x00, 0x21, /* movs r1, #0 */
0x41, 0x60, /* str r1, [r0, #4] */
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
retval = target_write_buffer(target, write_algorithm->address,
sizeof(stm32x_flash_write_code),
- (uint8_t *)stm32x_flash_write_code);
+ stm32x_flash_write_code);
if (retval != ERROR_OK)
return retval;
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- };
+ }
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
LOG_ERROR("flash memory write protected");
if (error != 0) {
- LOG_ERROR("flash write failed = %08x", error);
+ LOG_ERROR("flash write failed = %08" PRIx32, error);
/* Clear but report errors */
target_write_u32(target, STM32_FLASH_SR, error);
retval = ERROR_FAIL;
return retval;
}
-static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
static void setup_sector(struct flash_bank *bank, int start, int num, int size)
{
for (int i = start; i < (start + num) ; i++) {
+ assert(i < bank->num_sectors);
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i;
uint16_t flash_size_in_kb;
+ uint32_t flash_size_reg = 0x1FFF7A22;
+ uint16_t max_sector_size_in_kb = 128;
uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t base_address = 0x08000000;
switch (device_id & 0xfff) {
case 0x411:
case 0x413:
+ case 0x441:
max_flash_size_in_kb = 1024;
break;
case 0x419:
+ case 0x434:
max_flash_size_in_kb = 2048;
- stm32x_info->has_large_mem = true;
+ break;
+ case 0x423:
+ max_flash_size_in_kb = 256;
+ break;
+ case 0x431:
+ case 0x433:
+ case 0x421:
+ max_flash_size_in_kb = 512;
+ break;
+ case 0x458:
+ max_flash_size_in_kb = 128;
+ break;
+ case 0x449:
+ max_flash_size_in_kb = 1024;
+ max_sector_size_in_kb = 256;
+ flash_size_reg = 0x1FF0F442;
break;
default:
LOG_WARNING("Cannot identify target as a STM32 family.");
}
/* get flash size from target. */
- retval = target_read_u16(target, 0x1FFF7A22, &flash_size_in_kb);
+ retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
assert(flash_size_in_kb != 0xffff);
/* calculate numbers of pages */
- int num_pages = (flash_size_in_kb / 128) + 4;
+ int num_pages = (flash_size_in_kb / max_sector_size_in_kb) + 4;
+
+ /* Devices with > 1024 kiByte always are dual-banked */
+ if (flash_size_in_kb > 1024)
+ stm32x_info->has_large_mem = true;
- /* check for larger 2048 bytes devices */
+ /* F42x/43x 1024 kiByte devices have a dual bank option */
+ if ((device_id & 0xfff) == 0x419 && (flash_size_in_kb == 1024)) {
+ uint32_t optiondata;
+ retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("unable to read option bytes");
+ return retval;
+ }
+ if (optiondata & (1 << OPT_DB1M)) {
+ stm32x_info->has_large_mem = true;
+ LOG_INFO("Dual Bank 1024 kiB STM32F42x/43x found");
+ }
+ }
+
+ /* check for dual-banked devices */
if (stm32x_info->has_large_mem)
num_pages += 4;
bank->size = 0;
/* fixed memory */
- setup_sector(bank, 0, 4, 16 * 1024);
- setup_sector(bank, 4, 1, 64 * 1024);
-
- /* dynamic memory */
- setup_sector(bank, 4 + 1, MAX(12, num_pages) - 5, 128 * 1024);
+ setup_sector(bank, 0, 4, (max_sector_size_in_kb / 8) * 1024);
+ setup_sector(bank, 4, 1, (max_sector_size_in_kb / 2) * 1024);
if (stm32x_info->has_large_mem) {
-
- /* fixed memory for larger devices */
- setup_sector(bank, 12, 4, 16 * 1024);
- setup_sector(bank, 16, 1, 64 * 1024);
-
- /* dynamic memory for larger devices */
- setup_sector(bank, 16 + 1, num_pages - 5 - 12, 128 * 1024);
+ if (flash_size_in_kb == 1024) {
+ setup_sector(bank, 5, 3, 128 * 1024);
+ setup_sector(bank, 12, 4, 16 * 1024);
+ setup_sector(bank, 16, 1, 64 * 1024);
+ setup_sector(bank, 17, 3, 128 * 1024);
+ } else {
+ setup_sector(bank, 5, 7, 128 * 1024);
+ setup_sector(bank, 12, 4, 16 * 1024);
+ setup_sector(bank, 16, 1, 64 * 1024);
+ setup_sector(bank, 17, 7, 128 * 1024);
+ }
+ } else {
+ setup_sector(bank, 4 + 1, MIN(12, num_pages) - 5,
+ max_sector_size_in_kb * 1024);
}
-
for (i = 0; i < num_pages; i++) {
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 0;
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
{
- uint32_t device_id;
- int printed;
+ uint32_t dbgmcu_idcode;
/* read stm32 device id register */
- int retval = stm32x_get_device_id(bank, &device_id);
+ int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
if (retval != ERROR_OK)
return retval;
- if ((device_id & 0xfff) == 0x411) {
- printed = snprintf(buf, buf_size, "stm32f2x - Rev: ");
- buf += printed;
- buf_size -= printed;
+ uint16_t device_id = dbgmcu_idcode & 0xfff;
+ uint16_t rev_id = dbgmcu_idcode >> 16;
+ const char *device_str;
+ const char *rev_str = NULL;
- switch (device_id >> 16) {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
+ switch (device_id) {
+ case 0x411:
+ device_str = "STM32F2xx";
- case 0x2000:
- snprintf(buf, buf_size, "B");
- break;
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
+ case 0x2000:
+ rev_str = "B";
+ break;
- case 0x2001:
- snprintf(buf, buf_size, "Y");
- break;
+ case 0x1001:
+ rev_str = "Z";
+ break;
- case 0x2003:
- snprintf(buf, buf_size, "X");
- break;
+ case 0x2001:
+ rev_str = "Y";
+ break;
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ case 0x2003:
+ rev_str = "X";
+ break;
}
- } else if (((device_id & 0xfff) == 0x413) ||
- ((device_id & 0xfff) == 0x419)) {
- printed = snprintf(buf, buf_size, "stm32f4x - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16) {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x413:
+ case 0x419:
+ device_str = "STM32F4xx";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+
+ case 0x1003:
+ rev_str = "Y";
+ break;
+
+ case 0x1007:
+ rev_str = "1";
+ break;
+
+ case 0x2001:
+ rev_str = "3";
+ break;
}
- } else {
- snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
+ break;
+ case 0x421:
+ device_str = "STM32F446";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+ case 0x423:
+ case 0x431:
+ case 0x433:
+ case 0x458:
+ case 0x441:
+ device_str = "STM32F4xx (Low Power)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+ }
+ break;
+
+ case 0x449:
+ device_str = "STM32F7[4|5]x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+ }
+ break;
+ case 0x434:
+ device_str = "STM32F46x/F47x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ default:
+ snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
return ERROR_FAIL;
}
+ if (rev_str != NULL)
+ snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
+ else
+ snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
+
return ERROR_OK;
}
static int stm32x_mass_erase(struct flash_bank *bank)
{
int retval;
+ uint32_t flash_mer;
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = NULL;
/* mass erase flash memory */
if (stm32x_info->has_large_mem)
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_MER1);
+ flash_mer = FLASH_MER | FLASH_MER1;
else
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
+ flash_mer = FLASH_MER;
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
- FLASH_MER | FLASH_STRT);
+ flash_mer | FLASH_STRT);
if (retval != ERROR_OK)
return retval;
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