* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/***************************************************************************
#include "config.h"
#endif
-#include "lpc288x.h"
-#include "binarybuffer.h"
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#define LOAD_TIMER_ERASE 0
+#define LOAD_TIMER_WRITE 1
-#define LOAD_TIMER_ERASE 0
-#define LOAD_TIMER_WRITE 1
-
-#define FLASH_PAGE_SIZE 512
+#define FLASH_PAGE_SIZE 512
/* LPC288X control registers */
-#define DBGU_CIDR 0x8000507C
+#define DBGU_CIDR 0x8000507C
/* LPC288X flash registers */
-#define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
-#define F_STAT 0x80102004 /* Flash status register RO 0x45 */
-#define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
-#define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
-#define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0 */
-#define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
-#define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
-#define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
-#define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
-#define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
-#define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
-#define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power savings. R/W 1*/
-#define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from Power Down mode. R/W -*/
+#define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
+#define F_STAT 0x80102004 /* Flash status register RO 0x45 */
+#define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
+#define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
+#define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0
+ **/
+#define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
+#define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
+#define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
+#define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
+#define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
+#define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
+#define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power
+ *savings. R/W 1*/
+#define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from
+ *Power Down mode. R/W -*/
/* F_CTRL bits */
-#define FC_CS 0x0001
-#define FC_FUNC 0x0002
-#define FC_WEN 0x0004
-#define FC_RD_LATCH 0x0020
-#define FC_PROTECT 0x0080
-#define FC_SET_DATA 0x0400
-#define FC_RSSL 0x0800
-#define FC_PROG_REQ 0x1000
-#define FC_CLR_BUF 0x4000
-#define FC_LOAD_REQ 0x8000
+#define FC_CS 0x0001
+#define FC_FUNC 0x0002
+#define FC_WEN 0x0004
+#define FC_RD_LATCH 0x0020
+#define FC_PROTECT 0x0080
+#define FC_SET_DATA 0x0400
+#define FC_RSSL 0x0800
+#define FC_PROG_REQ 0x1000
+#define FC_CLR_BUF 0x4000
+#define FC_LOAD_REQ 0x8000
/* F_STAT bits */
-#define FS_DONE 0x0001
-#define FS_PROGGNT 0x0002
-#define FS_RDY 0x0004
-#define FS_ERR 0x0020
+#define FS_DONE 0x0001
+#define FS_PROGGNT 0x0002
+#define FS_RDY 0x0004
+#define FS_ERR 0x0020
/* F_PROG_TIME */
-#define FPT_TIME_MASK 0x7FFF
+#define FPT_TIME_MASK 0x7FFF
-#define FPT_ENABLE 0x8000
+#define FPT_ENABLE 0x8000
/* F_WAIT */
-#define FW_WAIT_STATES_MASK 0x00FF
-#define FW_SET_MASK 0xC000
+#define FW_WAIT_STATES_MASK 0x00FF
+#define FW_SET_MASK 0xC000
/* F_CLK_TIME */
#define FCT_CLK_DIV_MASK 0x0FFF
+struct lpc288x_flash_bank {
+ uint32_t working_area;
+ uint32_t working_area_size;
+
+ /* chip id register */
+ uint32_t cidr;
+ const char *target_name;
+ uint32_t cclk;
+
+ uint32_t sector_size_break;
+};
+
static uint32_t lpc288x_wait_status_busy(struct flash_bank *bank, int timeout);
static void lpc288x_load_timer(int erase, struct target *target);
static void lpc288x_set_flash_clk(struct flash_bank *bank);
{
uint32_t status;
struct target *target = bank->target;
- do
- {
+ do {
alive_sleep(1);
timeout--;
target_read_u32(target, F_STAT, &status);
} while (((status & FS_DONE) == 0) && timeout);
- if (timeout == 0)
- {
+ if (timeout == 0) {
LOG_DEBUG("Timedout!");
return ERROR_FLASH_OPERATION_FAILED;
}
uint32_t offset;
if (lpc288x_info->cidr == 0x0102100A)
- return ERROR_OK; /* already probed, multiple probes may cause memory leak, not allowed */
+ return ERROR_OK;/* already probed, multiple probes may cause memory leak, not
+ *allowed */
/* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr);
- if (cidr != 0x0102100A)
- {
- LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32 ")",cidr);
+ if (cidr != 0x0102100A) {
+ LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32 ")", cidr);
return ERROR_FLASH_OPERATION_FAILED;
}
bank->num_sectors = 23;
bank->sectors = malloc(sizeof(struct flash_sector) * 23);
- for (i = 0; i < 15; i++)
- {
+ for (i = 0; i < 15; i++) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = 64 * 1024;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
- for (i = 15; i < 23; i++)
- {
+ for (i = 15; i < 23; i++) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = 8 * 1024;
offset += bank->sectors[i].size;
return ERROR_OK;
}
+/* TODO: Revisit! Is it impossible to read protection status? */
static int lpc288x_protect_check(struct flash_bank *bank)
{
return ERROR_OK;
struct lpc288x_flash_bank *lpc288x_info;
if (CMD_ARGC < 6)
- {
- LOG_WARNING("incomplete flash_bank LPC288x configuration");
- return ERROR_FLASH_BANK_INVALID;
- }
+ return ERROR_COMMAND_SYNTAX_ERROR;
lpc288x_info = malloc(sizeof(struct lpc288x_flash_bank));
bank->driver_priv = lpc288x_info;
static void lpc288x_load_timer(int erase, struct target *target)
{
if (erase == LOAD_TIMER_ERASE)
- {
target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
- }
else
- {
target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
- }
}
static uint32_t lpc288x_system_ready(struct flash_bank *bank)
{
struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
if (lpc288x_info->cidr == 0)
- {
return ERROR_FLASH_BANK_NOT_PROBED;
- }
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
static int lpc288x_erase_check(struct flash_bank *bank)
{
uint32_t status = lpc288x_system_ready(bank); /* probed? halted? */
- if (status != ERROR_OK)
- {
+ if (status != ERROR_OK) {
LOG_INFO("Processor not halted/not probed");
return status;
}
int sector;
struct target *target = bank->target;
- status = lpc288x_system_ready(bank); /* probed? halted? */
+ status = lpc288x_system_ready(bank); /* probed? halted? */
if (status != ERROR_OK)
- {
return status;
- }
- if ((first < 0) || (last < first) || (last >= bank->num_sectors))
- {
+ if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
LOG_INFO("Bad sector range");
return ERROR_FLASH_SECTOR_INVALID;
}
/* Configure the flash controller timing */
lpc288x_set_flash_clk(bank);
- for (sector = first; sector <= last; sector++)
- {
+ for (sector = first; sector <= last; sector++) {
if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
- {
return ERROR_FLASH_OPERATION_FAILED;
- }
- lpc288x_load_timer(LOAD_TIMER_ERASE,target);
+ lpc288x_load_timer(LOAD_TIMER_ERASE, target);
target_write_u32(target, bank->sectors[sector].offset, 0x00);
target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS);
}
if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
- {
return ERROR_FLASH_OPERATION_FAILED;
- }
return ERROR_OK;
}
-static int lpc288x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
uint8_t page_buffer[FLASH_PAGE_SIZE];
- uint32_t status, source_offset,dest_offset;
+ uint32_t status, source_offset, dest_offset;
struct target *target = bank->target;
uint32_t bytes_remaining = count;
uint32_t first_sector, last_sector, sector, page;
/* probed? halted? */
status = lpc288x_system_ready(bank);
if (status != ERROR_OK)
- {
return status;
- }
/* Initialise search indices */
first_sector = last_sector = 0xffffffff;
/* validate the write range... */
- for (i = 0; i < bank->num_sectors; i++)
- {
+ for (i = 0; i < bank->num_sectors; i++) {
if ((offset >= bank->sectors[i].offset) &&
- (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
- (first_sector == 0xffffffff))
- {
+ (offset < (bank->sectors[i].offset + bank->sectors[i].size)) &&
+ (first_sector == 0xffffffff)) {
first_sector = i;
/* all writes must start on a sector boundary... */
- if (offset % bank->sectors[i].size)
- {
- LOG_INFO("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, bank->sectors[i].size);
+ if (offset % bank->sectors[i].size) {
+ LOG_INFO(
+ "offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
+ offset,
+ bank->sectors[i].size);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
}
if (((offset + count) > bank->sectors[i].offset) &&
- ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
- (last_sector == 0xffffffff))
- {
+ ((offset + count) <= (bank->sectors[i].offset + bank->sectors[i].size)) &&
+ (last_sector == 0xffffffff))
last_sector = i;
- }
}
/* Range check... */
- if (first_sector == 0xffffffff || last_sector == 0xffffffff)
- {
+ if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
return ERROR_FLASH_DST_OUT_OF_BANK;
}
source_offset = 0;
dest_offset = 0;
- for (sector = first_sector; sector <= last_sector; sector++)
- {
- for (page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++)
- {
- if (bytes_remaining == 0)
- {
+ for (sector = first_sector; sector <= last_sector; sector++) {
+ for (page = 0; page < bank->sectors[sector].size / FLASH_PAGE_SIZE; page++) {
+ if (bytes_remaining == 0) {
count = 0;
memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
- }
- else if (bytes_remaining < FLASH_PAGE_SIZE)
- {
+ } else if (bytes_remaining < FLASH_PAGE_SIZE) {
count = bytes_remaining;
memset(page_buffer, 0xFF, FLASH_PAGE_SIZE);
memcpy(page_buffer, &buffer[source_offset], count);
- }
- else
- {
+ } else {
count = FLASH_PAGE_SIZE;
memcpy(page_buffer, &buffer[source_offset], count);
}
/* Wait for flash to become ready */
if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
- {
return ERROR_FLASH_OPERATION_FAILED;
- }
/* fill flash data latches with 1's */
target_write_u32(target, F_CTRL, FC_CS | FC_SET_DATA | FC_WEN | FC_FUNC);
target_write_u32(target, F_CTRL, FC_CS | FC_WEN | FC_FUNC);
- /*would be better to use the clean target_write_buffer() interface but
- * it seems not to be a LOT slower....
- * bulk_write_memory() is no quicker :(*/
-#if 1
- if (target_write_memory(target, offset + dest_offset, 4, 128, page_buffer) != ERROR_OK)
- {
- LOG_ERROR("Write failed s %" PRIx32 " p %" PRIx32 "", sector, page);
- return ERROR_FLASH_OPERATION_FAILED;
- }
-#else
- if (target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE, page_buffer) != ERROR_OK)
- {
+
+ if (target_write_buffer(target, offset + dest_offset, FLASH_PAGE_SIZE,
+ page_buffer) != ERROR_OK) {
LOG_INFO("Write to flash buffer failed");
return ERROR_FLASH_OPERATION_FAILED;
}
-#endif
+
dest_offset += FLASH_PAGE_SIZE;
source_offset += count;
bytes_remaining -= count;
lpc288x_load_timer(LOAD_TIMER_WRITE, target);
- target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC | FC_CS);
+ target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC |
+ FC_CS);
}
}
int retval;
if (lpc288x_info->cidr != 0)
- {
- return ERROR_OK; /* already probed */
- }
+ return ERROR_OK;/* already probed */
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
return ERROR_OK;
}
-static int lpc288x_info(struct flash_bank *bank, char *buf, int buf_size)
-{
- snprintf(buf, buf_size, "lpc288x flash driver");
- return ERROR_OK;
-}
-
static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last)
{
int lockregion, status;
/* probed? halted? */
status = lpc288x_system_ready(bank);
if (status != ERROR_OK)
- {
return status;
- }
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
- {
return ERROR_FLASH_SECTOR_INVALID;
- }
/* Configure the flash controller timing */
lpc288x_set_flash_clk(bank);
- for (lockregion = first; lockregion <= last; lockregion++)
- {
- if (set)
- {
+ for (lockregion = first; lockregion <= last; lockregion++) {
+ if (set) {
/* write an odd value to base addy to protect... */
value = 0x01;
- }
- else
- {
+ } else {
/* write an even value to base addy to unprotect... */
value = 0x00;
}
target_write_u32(target, bank->sectors[lockregion].offset, value);
- target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC | FC_CS);
+ target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC |
+ FC_CS);
}
return ERROR_OK;
}
struct flash_driver lpc288x_flash = {
- .name = "lpc288x",
- .flash_bank_command = &lpc288x_flash_bank_command,
- .erase = &lpc288x_erase,
- .protect = &lpc288x_protect,
- .write = &lpc288x_write,
- .probe = &lpc288x_probe,
- .auto_probe = &lpc288x_probe,
- .erase_check = &lpc288x_erase_check,
- .protect_check = &lpc288x_protect_check,
- .info = &lpc288x_info,
- };
+ .name = "lpc288x",
+ .flash_bank_command = lpc288x_flash_bank_command,
+ .erase = lpc288x_erase,
+ .protect = lpc288x_protect,
+ .write = lpc288x_write,
+ .read = default_flash_read,
+ .probe = lpc288x_probe,
+ .auto_probe = lpc288x_probe,
+ .erase_check = lpc288x_erase_check,
+ .protect_check = lpc288x_protect_check,
+ .free_driver_priv = default_flash_free_driver_priv,
+};
Code Review / openocd.git / blobdiff