+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2014 Nemui Trinomius *
* nemuisan_kawausogasuki@live.jp *
* *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ * Copyright (C) 2021 Doug Brunner *
+ * doug.a.brunner@gmail.com *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#define EFM32_FLASH_WDATAREADY_TMO 100
#define EFM32_FLASH_WRITE_TMO 100
+#define EFM32_FLASH_BASE 0
+
/* size in bytes, not words; must fit all Gecko devices */
-#define LOCKBITS_PAGE_SZ 512
+#define LOCKWORDS_SZ 512
#define EFM32_MSC_INFO_BASE 0x0fe00000
#define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
#define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
+#define EFM32_MSC_LOCK_BITS_EXTRA (EFM32_MSC_LOCK_BITS+LOCKWORDS_SZ)
#define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
/* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
#define EFM32_MSC_REG_LOCK_SERIES1 0x040
#define EFM32_MSC_LOCK_LOCKKEY 0x1b71
+enum efm32_bank_index {
+ EFM32_BANK_INDEX_MAIN,
+ EFM32_BANK_INDEX_USER_DATA,
+ EFM32_BANK_INDEX_LOCK_BITS,
+ EFM32_N_BANKS
+};
+
+static int efm32x_get_bank_index(target_addr_t base)
+{
+ switch (base) {
+ case EFM32_FLASH_BASE:
+ return EFM32_BANK_INDEX_MAIN;
+ case EFM32_MSC_USER_DATA:
+ return EFM32_BANK_INDEX_USER_DATA;
+ case EFM32_MSC_LOCK_BITS:
+ return EFM32_BANK_INDEX_LOCK_BITS;
+ default:
+ return ERROR_FAIL;
+ }
+}
+
struct efm32_family_data {
int family_id;
const char *name;
uint32_t msc_regbase;
};
-struct efm32x_flash_bank {
- int probed;
- uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
- uint32_t reg_base;
- uint32_t reg_lock;
-};
-
struct efm32_info {
const struct efm32_family_data *family_data;
uint16_t flash_sz_kib;
uint16_t page_size;
};
+struct efm32x_flash_chip {
+ struct efm32_info info;
+ bool probed[EFM32_N_BANKS];
+ uint32_t lb_page[LOCKWORDS_SZ/4];
+ uint32_t reg_base;
+ uint32_t reg_lock;
+ uint32_t refcount;
+};
+
static const struct efm32_family_data efm32_families[] = {
{ 16, "EFR32MG1P Mighty", .series = 1 },
{ 17, "EFR32MG1B Mighty", .series = 1 },
{ 18, "EFR32MG1V Mighty", .series = 1 },
- { 19, "EFR32MG1P Blue", .series = 1 },
- { 20, "EFR32MG1B Blue", .series = 1 },
- { 21, "EFR32MG1V Blue", .series = 1 },
+ { 19, "EFR32BG1P Blue", .series = 1 },
+ { 20, "EFR32BG1B Blue", .series = 1 },
+ { 21, "EFR32BG1V Blue", .series = 1 },
{ 25, "EFR32FG1P Flex", .series = 1 },
{ 26, "EFR32FG1B Flex", .series = 1 },
{ 27, "EFR32FG1V Flex", .series = 1 },
{ 43, "EFR32BG13P Blue", .series = 1 },
{ 44, "EFR32BG13B Blue", .series = 1 },
{ 45, "EFR32BG13V Blue", .series = 1 },
+ { 46, "EFR32ZG13P Zen", .series = 1 },
{ 49, "EFR32FG13P Flex", .series = 1 },
{ 50, "EFR32FG13B Flex", .series = 1 },
{ 51, "EFR32FG13V Flex", .series = 1 },
{ 55, "EFR32BG14P Blue", .series = 1 },
{ 56, "EFR32BG14B Blue", .series = 1 },
{ 57, "EFR32BG14V Blue", .series = 1 },
+ { 58, "EFR32ZG14P Zen", .series = 1 },
{ 61, "EFR32FG14P Flex", .series = 1 },
{ 62, "EFR32FG14B Flex", .series = 1 },
{ 63, "EFR32FG14V Flex", .series = 1 },
{ 89, "EFM32PG13B Pearl", .series = 1 },
{ 91, "EFM32JG13B Jade", .series = 1 },
{ 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
- { 103, "EFM32TG11B Tiny", .series = 1 },
+ { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
+ { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
{ 120, "EZR32WG Wonder", .series = 0 },
{ 121, "EZR32LG Leopard", .series = 0 },
{ 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
};
+const struct flash_driver efm32_flash;
-static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count);
+static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t addr, uint32_t count);
+
+static int efm32x_write_only_lockbits(struct flash_bank *bank);
static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
{
static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
uint32_t *value)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
uint32_t base = efm32x_info->reg_base;
return target_read_u32(bank->target, base + offset, value);
static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
uint32_t value)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
uint32_t base = efm32x_info->reg_base;
return target_write_u32(bank->target, base + offset, value);
}
-static int efm32x_read_info(struct flash_bank *bank,
- struct efm32_info *efm32_info)
+static int efm32x_read_info(struct flash_bank *bank)
{
int ret;
- uint32_t cpuid = 0;
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+ struct efm32_info *efm32_info = &(efm32x_info->info);
memset(efm32_info, 0, sizeof(struct efm32_info));
- ret = target_read_u32(bank->target, CPUID, &cpuid);
- if (ERROR_OK != ret)
- return ret;
-
- if (((cpuid >> 4) & 0xfff) == 0xc23) {
- /* Cortex-M3 device */
- } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
- /* Cortex-M4 device (WONDER GECKO) */
- } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
- /* Cortex-M0+ device */
- } else {
- LOG_ERROR("Target is not Cortex-Mx Device");
- return ERROR_FAIL;
- }
-
ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
efm32_info->family_data = &efm32_families[i];
}
- if (efm32_info->family_data == NULL) {
+ if (!efm32_info->family_data) {
LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
return ERROR_FAIL;
}
uint8_t pg_size = 0;
ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
&pg_size);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
return ERROR_OK;
}
-/*
- * Helper to create a human friendly string describing a part
- */
-static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
-{
- int printed = 0;
- printed = snprintf(buf, buf_size, "%s Gecko, rev %d",
- info->family_data->name, info->prod_rev);
-
- if (printed >= buf_size)
- return ERROR_BUF_TOO_SMALL;
-
- return ERROR_OK;
-}
-
-/* flash bank efm32 <base> <size> 0 0 <target#>
- */
+/* flash bank efm32 <base> <size> 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
{
- struct efm32x_flash_bank *efm32x_info;
+ struct efm32x_flash_chip *efm32x_info = NULL;
if (CMD_ARGC < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
- efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
+ int bank_index = efm32x_get_bank_index(bank->base);
+ if (bank_index < 0) {
+ LOG_ERROR("Flash bank with base address %" PRIx32 " is not supported",
+ (uint32_t) bank->base);
+ return ERROR_FAIL;
+ }
+
+ /* look for an existing flash structure matching target */
+ for (struct flash_bank *bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
+ if (bank_iter->driver == &efm32_flash
+ && bank_iter->target == bank->target
+ && bank->driver_priv) {
+ efm32x_info = bank->driver_priv;
+ break;
+ }
+ }
+
+ if (!efm32x_info) {
+ /* target not matched, make a new one */
+ efm32x_info = calloc(1, sizeof(struct efm32x_flash_chip));
+
+ memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
+ }
+ ++efm32x_info->refcount;
bank->driver_priv = efm32x_info;
- efm32x_info->probed = 0;
- memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
return ERROR_OK;
}
+/**
+ * Remove flash structure corresponding to this bank,
+ * if and only if it's not used by any others
+ */
+static void efm32x_free_driver_priv(struct flash_bank *bank)
+{
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+
+ if (efm32x_info) {
+ /* Use ref count to determine if it can be freed; scanning bank list doesn't work,
+ * because this function can be called after some banks in the list have been
+ * already destroyed */
+ --efm32x_info->refcount;
+ if (efm32x_info->refcount == 0) {
+ free(efm32x_info);
+ bank->driver_priv = NULL;
+ }
+ }
+}
+
/* set or reset given bits in a register */
static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
uint32_t bitmask, int set)
uint32_t reg_val = 0;
ret = efm32x_read_reg_u32(bank, reg, ®_val);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
if (set)
static int efm32x_msc_lock(struct flash_bank *bank, int lock)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
}
while (1) {
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
break;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
- if (((status & wait_mask) == 0) && (0 == wait_for_set))
+ if (((status & wait_mask) == 0) && (wait_for_set == 0))
break;
else if (((status & wait_mask) != 0) && wait_for_set)
break;
*/
int ret = 0;
uint32_t status = 0;
- addr += bank->base;
LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
EFM32_MSC_STATUS_BUSY_MASK, 0);
}
-static int efm32x_erase(struct flash_bank *bank, int first, int last)
+static int efm32x_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i = 0;
int ret = 0;
- if (TARGET_HALTED != target->state) {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
efm32x_msc_lock(bank, 0);
ret = efm32x_set_wren(bank, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to enable MSC write");
return ret;
}
- for (i = first; i <= last; i++) {
- ret = efm32x_erase_page(bank, bank->sectors[i].offset);
- if (ERROR_OK != ret)
+ for (unsigned int i = first; i <= last; i++) {
+ ret = efm32x_erase_page(bank, bank->base + bank->sectors[i].offset);
+ if (ret != ERROR_OK)
LOG_ERROR("Failed to erase page %d", i);
}
ret = efm32x_set_wren(bank, 0);
efm32x_msc_lock(bank, 1);
+ if (ret != ERROR_OK)
+ return ret;
+
+ if (bank->base == EFM32_MSC_LOCK_BITS) {
+ ret = efm32x_write_only_lockbits(bank);
+ if (ret != ERROR_OK)
+ LOG_ERROR("Failed to restore lockbits after erase");
+ }
return ret;
}
static int efm32x_read_lock_data(struct flash_bank *bank)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
struct target *target = bank->target;
- int i = 0;
int data_size = 0;
uint32_t *ptr = NULL;
int ret = 0;
ptr = efm32x_info->lb_page;
- for (i = 0; i < data_size; i++, ptr++) {
+ for (int i = 0; i < data_size; i++, ptr++) {
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read PLW %d", i);
return ret;
}
/* ULW, word 126 */
ptr = efm32x_info->lb_page + 126;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read ULW");
return ret;
}
/* DLW, word 127 */
ptr = efm32x_info->lb_page + 127;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read DLW");
return ret;
}
/* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 125;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read MLW");
return ret;
}
/* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 124;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read ALW");
return ret;
}
/* CLW1, word 123, present in EFR32 */
ptr = efm32x_info->lb_page + 123;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read CLW1");
return ret;
}
/* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
ptr = efm32x_info->lb_page + 122;
ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read CLW0");
return ret;
}
return ERROR_OK;
}
+static int efm32x_write_only_lockbits(struct flash_bank *bank)
+{
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+ return efm32x_priv_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
+}
+
static int efm32x_write_lock_data(struct flash_bank *bank)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
int ret = 0;
+ /* Preserve any data written to the high portion of the lockbits page */
+ assert(efm32x_info->info.page_size >= LOCKWORDS_SZ);
+ uint32_t extra_bytes = efm32x_info->info.page_size - LOCKWORDS_SZ;
+ uint8_t *extra_data = NULL;
+ if (extra_bytes) {
+ extra_data = malloc(extra_bytes);
+ ret = target_read_buffer(bank->target, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes, extra_data);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to read extra contents of LB page");
+ free(extra_data);
+ return ret;
+ }
+ }
+
ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to erase LB page");
+ if (extra_data)
+ free(extra_data);
return ret;
}
- return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
- LOCKBITS_PAGE_SZ);
+ if (extra_data) {
+ ret = efm32x_priv_write(bank, extra_data, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes);
+ free(extra_data);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to restore extra contents of LB page");
+ return ret;
+ }
+ }
+
+ return efm32x_write_only_lockbits(bank);
}
static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
- uint32_t dw = efm32x_info->lb_page[page >> 5];
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+ uint32_t dw = 0;
uint32_t mask = 0;
- mask = 1 << (page & 0x1f);
+ switch (bank->base) {
+ case EFM32_FLASH_BASE:
+ dw = efm32x_info->lb_page[page >> 5];
+ mask = 1 << (page & 0x1f);
+ break;
+ case EFM32_MSC_USER_DATA:
+ dw = efm32x_info->lb_page[126];
+ mask = 0x1;
+ break;
+ case EFM32_MSC_LOCK_BITS:
+ dw = efm32x_info->lb_page[126];
+ mask = 0x2;
+ break;
+ }
return (dw & mask) ? 0 : 1;
}
static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+
+ if (bank->base != EFM32_FLASH_BASE) {
+ LOG_ERROR("Locking user and lockbits pages is not supported yet");
+ return ERROR_FAIL;
+ }
+
uint32_t *dw = &efm32x_info->lb_page[page >> 5];
uint32_t mask = 0;
return ERROR_OK;
}
-static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
+static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
- int i = 0;
int ret = 0;
- if (!set) {
- LOG_ERROR("Erase device data to reset page locks");
- return ERROR_FAIL;
- }
-
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- for (i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
ret = efm32x_set_page_lock(bank, i, set);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to set lock on page %d", i);
return ret;
}
}
ret = efm32x_write_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return ret;
}
}
static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
- uint32_t offset, uint32_t count)
+ uint32_t address, uint32_t count)
{
struct target *target = bank->target;
uint32_t buffer_size = 16384;
struct working_area *write_algorithm;
struct working_area *source;
- uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
struct armv7m_algorithm armv7m_info;
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
int ret = ERROR_OK;
/* see contrib/loaders/flash/efm32.S for src */
keep_alive();
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
- if (ERROR_OK != ret)
+ if (ret != ERROR_OK)
return ret;
LOG_DEBUG("status 0x%" PRIx32, status);
ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for WDATAREADY failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WDATA write failed");
return ret;
}
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_WRITEONCE_MASK);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("WRITECMD write failed");
return ret;
}
ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
EFM32_MSC_STATUS_BUSY_MASK, 0);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Wait for BUSY failed");
return ret;
}
return ERROR_OK;
}
-static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
+static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t addr, uint32_t count)
{
struct target *target = bank->target;
uint8_t *new_buffer = NULL;
return ERROR_TARGET_NOT_HALTED;
}
- if (offset & 0x3) {
- LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
- "alignment", offset);
+ if (addr & 0x3) {
+ LOG_ERROR("addr 0x%" PRIx32 " breaks required 4-byte "
+ "alignment", addr);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
uint32_t old_count = count;
count = (old_count | 3) + 1;
new_buffer = malloc(count);
- if (new_buffer == NULL) {
+ if (!new_buffer) {
LOG_ERROR("odd number of bytes to write and no memory "
"for padding buffer");
return ERROR_FAIL;
goto cleanup;
/* try using a block write */
- retval = efm32x_write_block(bank, buffer, offset, words_remaining);
+ retval = efm32x_write_block(bank, buffer, addr, words_remaining);
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
/* if block write failed (no sufficient working area),
uint32_t value;
memcpy(&value, buffer, sizeof(uint32_t));
- retval = efm32x_write_word(bank, offset, value);
+ retval = efm32x_write_word(bank, addr, value);
if (retval != ERROR_OK)
goto reset_pg_and_lock;
words_remaining--;
buffer += 4;
- offset += 4;
+ addr += 4;
}
}
retval = retval2;
cleanup:
- if (new_buffer)
- free(new_buffer);
-
+ free(new_buffer);
return retval;
}
+static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
+ LOG_ERROR("Cannot write to lock words");
+ return ERROR_FAIL;
+ }
+ return efm32x_priv_write(bank, buffer, bank->base + offset, count);
+}
+
static int efm32x_probe(struct flash_bank *bank)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
- struct efm32_info efm32_mcu_info;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+ struct efm32_info *efm32_mcu_info = &(efm32x_info->info);
int ret;
- int i;
- uint32_t base_address = 0x00000000;
- char buf[256];
- efm32x_info->probed = 0;
- memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
+ int bank_index = efm32x_get_bank_index(bank->base);
+ assert(bank_index >= 0);
- ret = efm32x_read_info(bank, &efm32_mcu_info);
- if (ERROR_OK != ret)
- return ret;
+ efm32x_info->probed[bank_index] = false;
+ memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
- ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
- if (ERROR_OK != ret)
+ ret = efm32x_read_info(bank);
+ if (ret != ERROR_OK)
return ret;
- LOG_INFO("detected part: %s", buf);
- LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
- LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
-
- assert(0 != efm32_mcu_info.page_size);
-
- int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
- efm32_mcu_info.page_size;
-
- assert(num_pages > 0);
+ LOG_INFO("detected part: %s Gecko, rev %d",
+ efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
+ LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
+ LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
- }
-
- bank->base = base_address;
- bank->size = (num_pages * efm32_mcu_info.page_size);
- bank->num_sectors = num_pages;
+ assert(efm32_mcu_info->page_size != 0);
- ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
- LOG_ERROR("Failed to read LB data");
- return ret;
- }
+ free(bank->sectors);
+ bank->sectors = NULL;
- bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ if (bank->base == EFM32_FLASH_BASE) {
+ bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 /
+ efm32_mcu_info->page_size;
+ assert(bank->num_sectors > 0);
- for (i = 0; i < num_pages; i++) {
- bank->sectors[i].offset = i * efm32_mcu_info.page_size;
- bank->sectors[i].size = efm32_mcu_info.page_size;
+ ret = efm32x_read_lock_data(bank);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to read LB data");
+ return ret;
+ }
+ } else
+ bank->num_sectors = 1;
+ bank->size = bank->num_sectors * efm32_mcu_info->page_size;
+ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+
+ for (uint32_t i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = i * efm32_mcu_info->page_size;
+ bank->sectors[i].size = efm32_mcu_info->page_size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
- efm32x_info->probed = 1;
+ efm32x_info->probed[bank_index] = true;
return ERROR_OK;
}
static int efm32x_auto_probe(struct flash_bank *bank)
{
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
- if (efm32x_info->probed)
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+
+ int bank_index = efm32x_get_bank_index(bank->base);
+ assert(bank_index >= 0);
+
+ if (efm32x_info->probed[bank_index])
return ERROR_OK;
return efm32x_probe(bank);
}
{
struct target *target = bank->target;
int ret = 0;
- int i = 0;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
}
ret = efm32x_read_lock_data(bank);
- if (ERROR_OK != ret) {
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read LB data");
return ret;
}
- assert(NULL != bank->sectors);
+ assert(bank->sectors);
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
return ERROR_OK;
}
-static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- struct efm32_info info;
- int ret = 0;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+ int ret;
- ret = efm32x_read_info(bank, &info);
- if (ERROR_OK != ret) {
+ ret = efm32x_read_info(bank);
+ if (ret != ERROR_OK) {
LOG_ERROR("Failed to read EFM32 info");
return ret;
}
- return efm32x_decode_info(&info, buf, buf_size);
+ command_print_sameline(cmd, "%s Gecko, rev %d", efm32x_info->info.family_data->name,
+ efm32x_info->info.prod_rev);
+ return ERROR_OK;
}
COMMAND_HANDLER(efm32x_handle_debuglock_command)
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
- struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
target = bank->target;
*ptr = 0;
retval = efm32x_write_lock_data(bank);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Failed to write LB page");
return retval;
}
.erase_check = default_flash_blank_check,
.protect_check = efm32x_protect_check,
.info = get_efm32x_info,
- .free_driver_priv = default_flash_free_driver_priv,
+ .free_driver_priv = efm32x_free_driver_priv,
};
Code Review / openocd.git / blobdiff