#include "imp.h"
#include "helper/binarybuffer.h"
+#include <target/cortex_m.h>
+
#define SAMD_NUM_SECTORS 16
#define SAMD_PAGE_SIZE_MAX 1024
#define SAMD_DSU 0x41002000 /* Device Service Unit */
#define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
+#define SAMD_DSU_STATUSA 1 /* DSU status register */
#define SAMD_DSU_DID 0x18 /* Device ID register */
#define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
#define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
#define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
+/* NVMCTRL bits */
+#define SAMD_NVM_CTRLB_MANW 0x80
+
/* Known identifiers */
#define SAMD_PROCESSOR_M0 0x01
#define SAMD_FAMILY_D 0x00
+#define SAMD_FAMILY_L 0x01
+#define SAMD_FAMILY_C 0x02
#define SAMD_SERIES_20 0x00
#define SAMD_SERIES_21 0x01
#define SAMD_SERIES_10 0x02
#define SAMD_SERIES_11 0x03
+/* Device ID macros */
+#define SAMD_GET_PROCESSOR(id) (id >> 28)
+#define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
+#define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
+#define SAMD_GET_DEVSEL(id) (id & 0xFF)
+
struct samd_part {
uint8_t id;
const char *name;
{ 0x1E, "SAMR21E16A", 64, 32 },
};
+/* Known SAML21 parts. */
+static const struct samd_part saml21_parts[] = {
+ { 0x00, "SAML21J18A", 256, 32 },
+ { 0x01, "SAML21J17A", 128, 16 },
+ { 0x02, "SAML21J16A", 64, 8 },
+ { 0x05, "SAML21G18A", 256, 32 },
+ { 0x06, "SAML21G17A", 128, 16 },
+ { 0x07, "SAML21G16A", 64, 8 },
+ { 0x0A, "SAML21E18A", 256, 32 },
+ { 0x0B, "SAML21E17A", 128, 16 },
+ { 0x0C, "SAML21E16A", 64, 8 },
+ { 0x0D, "SAML21E15A", 32, 4 },
+ { 0x0F, "SAML21J18B", 256, 32 },
+ { 0x10, "SAML21J17B", 128, 16 },
+ { 0x11, "SAML21J16B", 64, 8 },
+ { 0x14, "SAML21G18B", 256, 32 },
+ { 0x15, "SAML21G17B", 128, 16 },
+ { 0x16, "SAML21G16B", 64, 8 },
+ { 0x19, "SAML21E18B", 256, 32 },
+ { 0x1A, "SAML21E17B", 128, 16 },
+ { 0x1B, "SAML21E16B", 64, 8 },
+ { 0x1C, "SAML21E15B", 32, 4 },
+};
+
+/* Known SAMC20 parts. */
+static const struct samd_part samc20_parts[] = {
+ { 0x00, "SAMC20J18A", 256, 32 },
+ { 0x01, "SAMC20J17A", 128, 16 },
+ { 0x02, "SAMC20J16A", 64, 8 },
+ { 0x03, "SAMC20J15A", 32, 4 },
+ { 0x05, "SAMC20G18A", 256, 32 },
+ { 0x06, "SAMC20G17A", 128, 16 },
+ { 0x07, "SAMC20G16A", 64, 8 },
+ { 0x08, "SAMC20G15A", 32, 4 },
+ { 0x0A, "SAMC20E18A", 256, 32 },
+ { 0x0B, "SAMC20E17A", 128, 16 },
+ { 0x0C, "SAMC20E16A", 64, 8 },
+ { 0x0D, "SAMC20E15A", 32, 4 },
+};
+
+/* Known SAMC21 parts. */
+static const struct samd_part samc21_parts[] = {
+ { 0x00, "SAMC21J18A", 256, 32 },
+ { 0x01, "SAMC21J17A", 128, 16 },
+ { 0x02, "SAMC21J16A", 64, 8 },
+ { 0x03, "SAMC21J15A", 32, 4 },
+ { 0x05, "SAMC21G18A", 256, 32 },
+ { 0x06, "SAMC21G17A", 128, 16 },
+ { 0x07, "SAMC21G16A", 64, 8 },
+ { 0x08, "SAMC21G15A", 32, 4 },
+ { 0x0A, "SAMC21E18A", 256, 32 },
+ { 0x0B, "SAMC21E17A", 128, 16 },
+ { 0x0C, "SAMC21E16A", 64, 8 },
+ { 0x0D, "SAMC21E15A", 32, 4 },
+};
/* Each family of parts contains a parts table in the DEVSEL field of DID. The
* processor ID, family ID, and series ID are used to determine which exact
samd10_parts, ARRAY_SIZE(samd10_parts) },
{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
samd11_parts, ARRAY_SIZE(samd11_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
+ saml21_parts, ARRAY_SIZE(saml21_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
+ samc20_parts, ARRAY_SIZE(samc20_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
+ samc21_parts, ARRAY_SIZE(samc21_parts) },
};
struct samd_info {
static struct samd_info *samd_chips;
+
+
static const struct samd_part *samd_find_part(uint32_t id)
{
- uint8_t processor = (id >> 28);
- uint8_t family = (id >> 24) & 0x0F;
- uint8_t series = (id >> 16) & 0xFF;
- uint8_t devsel = id & 0xFF;
+ uint8_t processor = SAMD_GET_PROCESSOR(id);
+ uint8_t family = SAMD_GET_FAMILY(id);
+ uint8_t series = SAMD_GET_SERIES(id);
+ uint8_t devsel = SAMD_GET_DEVSEL(id);
for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
if (samd_families[i].processor == processor &&
static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
{
+ int res;
+
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- /* Read current configuration. */
- uint16_t tmp = 0;
- int res = target_read_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB,
- &tmp);
- if (res != ERROR_OK)
- return res;
-
- /* Set cache disable. */
- res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB,
- tmp | (1<<18));
- if (res != ERROR_OK)
- return res;
-
/* Issue the NVM command */
- int res_cmd = target_write_u16(target,
+ res = target_write_u16(target,
SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
-
- /* Try to restore configuration, regardless of NVM command write
- * status. */
- res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, tmp);
-
- if (res_cmd != ERROR_OK)
- return res_cmd;
-
if (res != ERROR_OK)
return res;
return ERROR_FLASH_OPERATION_FAILED;
}
- if (bank->sectors[s].is_erased != 1) {
- /* For each row in that sector */
- for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
- res = samd_erase_row(bank->target, r * chip->page_size * 4);
- if (res != ERROR_OK) {
- LOG_ERROR("SAMD: failed to erase sector %d", s);
- return res;
- }
+ /* For each row in that sector */
+ for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
+ res = samd_erase_row(bank->target, r * chip->page_size * 4);
+ if (res != ERROR_OK) {
+ LOG_ERROR("SAMD: failed to erase sector %d", s);
+ return res;
}
-
- bank->sectors[s].is_erased = 1;
}
}
return ERROR_OK;
}
-static struct flash_sector *samd_find_sector_by_address(struct flash_bank *bank, uint32_t address)
-{
- struct samd_info *chip = (struct samd_info *)bank->driver_priv;
- for (int i = 0; i < bank->num_sectors; i++) {
- if (bank->sectors[i].offset <= address &&
- address < bank->sectors[i].offset + chip->sector_size)
- return &bank->sectors[i];
- }
- return NULL;
-}
-
-/* Write an entire row (four pages) from host buffer 'buf' to row-aligned
- * 'address' in the Flash. */
-static int samd_write_row(struct flash_bank *bank, uint32_t address,
- const uint8_t *buf)
+static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
{
int res;
+ uint32_t nvm_ctrlb;
+ uint32_t address;
+ uint32_t pg_offset;
+ uint32_t nb;
+ uint32_t nw;
struct samd_info *chip = (struct samd_info *)bank->driver_priv;
+ uint8_t *pb = NULL;
+ bool manual_wp;
- struct flash_sector *sector = samd_find_sector_by_address(bank, address);
-
- if (!sector) {
- LOG_ERROR("Can't find sector corresponding to address 0x%08" PRIx32, address);
- return ERROR_FLASH_OPERATION_FAILED;
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
}
- if (sector->is_protected) {
- LOG_ERROR("Trying to write to a protected sector at 0x%08" PRIx32, address);
- return ERROR_FLASH_OPERATION_FAILED;
+ if (!chip->probed) {
+ if (samd_probe(bank) != ERROR_OK)
+ return ERROR_FLASH_BANK_NOT_PROBED;
}
- /* Erase the row that we'll be writing to */
- res = samd_erase_row(bank->target, address);
+ /* Check if we need to do manual page write commands */
+ res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
+
if (res != ERROR_OK)
return res;
- /* Now write the pages in this row. */
- for (unsigned int i = 0; i < 4; i++) {
- bool error;
+ if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
+ manual_wp = true;
+ else
+ manual_wp = false;
- /* Write the page contents to the target's page buffer. A page write
- * is issued automatically once the last location is written in the
- * page buffer (ie: a complete page has been written out). */
- res = target_write_memory(bank->target, address, 4,
- chip->page_size / 4, buf);
- if (res != ERROR_OK) {
- LOG_ERROR("%s: %d", __func__, __LINE__);
- return res;
- }
-
- /* Access through AHB is stalled while flash is being programmed */
- usleep(200);
-
- error = samd_check_error(bank->target);
- if (error)
- return ERROR_FAIL;
-
- /* Next page */
- address += chip->page_size;
- buf += chip->page_size;
- }
-
- sector->is_erased = 0;
-
- return res;
-}
-
-/* Write partial contents into row-aligned 'address' on the Flash from host
- * buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
-static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
- const uint8_t *buf, uint32_t row_offset, uint32_t nb)
-{
- int res;
- struct samd_info *chip = (struct samd_info *)bank->driver_priv;
- uint32_t row_size = chip->page_size * 4;
- uint8_t *rb = malloc(row_size);
- if (!rb)
- return ERROR_FAIL;
-
- assert(row_offset + nb < row_size);
- assert((address % row_size) == 0);
-
- /* Retrieve the full row contents from Flash */
- res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
+ res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
if (res != ERROR_OK) {
- free(rb);
+ LOG_ERROR("%s: %d", __func__, __LINE__);
return res;
}
- /* Insert our partial row over the data from Flash */
- memcpy(rb + (row_offset % row_size), buf, nb);
+ while (count) {
+ nb = chip->page_size - offset % chip->page_size;
+ if (count < nb)
+ nb = count;
- /* Write the row back out */
- res = samd_write_row(bank, address, rb);
- free(rb);
+ address = bank->base + offset;
+ pg_offset = offset % chip->page_size;
- return res;
-}
+ if (offset % 4 || (offset + nb) % 4) {
+ /* Either start or end of write is not word aligned */
+ if (!pb) {
+ pb = malloc(chip->page_size);
+ if (!pb)
+ return ERROR_FAIL;
+ }
-static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
-{
- int res;
- uint32_t address;
- uint32_t nb = 0;
- struct samd_info *chip = (struct samd_info *)bank->driver_priv;
- uint32_t row_size = chip->page_size * 4;
+ /* Set temporary page buffer to 0xff and overwrite the relevant part */
+ memset(pb, 0xff, chip->page_size);
+ memcpy(pb + pg_offset, buffer, nb);
- if (bank->target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
+ /* Align start address to a word boundary */
+ address -= offset % 4;
+ pg_offset -= offset % 4;
+ assert(pg_offset % 4 == 0);
- return ERROR_TARGET_NOT_HALTED;
- }
+ /* Extend length to whole words */
+ nw = (nb + offset % 4 + 3) / 4;
+ assert(pg_offset + 4 * nw <= chip->page_size);
- if (!chip->probed) {
- if (samd_probe(bank) != ERROR_OK)
- return ERROR_FLASH_BANK_NOT_PROBED;
- }
+ /* Now we have original data extended by 0xff bytes
+ * to the nearest word boundary on both start and end */
+ res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
+ } else {
+ assert(nb % 4 == 0);
+ nw = nb / 4;
+ assert(pg_offset + 4 * nw <= chip->page_size);
- if (offset % row_size) {
- /* We're starting at an unaligned offset so we'll write a partial row
- * comprising that offset and up to the end of that row. */
- nb = row_size - (offset % row_size);
- if (nb > count)
- nb = count;
- } else if (count < row_size) {
- /* We're writing an aligned but partial row. */
- nb = count;
- }
+ /* Word aligned data, use direct write from buffer */
+ res = target_write_memory(bank->target, address, 4, nw, buffer);
+ }
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ goto free_pb;
+ }
- address = (offset / row_size) * row_size + bank->base;
+ /* Devices with errata 13134 have automatic page write enabled by default
+ * For other devices issue a write page CMD to the NVM
+ * If the page has not been written up to the last word
+ * then issue CMD_WP always */
+ if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
+ res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ goto free_pb;
+ }
+ }
- if (nb > 0) {
- res = samd_write_row_partial(bank, address, buffer,
- offset % row_size, nb);
- if (res != ERROR_OK)
- return res;
+ /* Access through AHB is stalled while flash is being programmed */
+ usleep(200);
+
+ if (samd_check_error(bank->target)) {
+ LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
+ res = ERROR_FAIL;
+ goto free_pb;
+ }
- /* We're done with the row contents */
+ /* We're done with the page contents */
count -= nb;
offset += nb;
- buffer += row_size;
+ buffer += nb;
}
- /* There's at least one aligned row to write out. */
- if (count >= row_size) {
- int nr = count / row_size + ((count % row_size) ? 1 : 0);
- unsigned int r = 0;
-
- for (unsigned int i = address / row_size;
- (i < (address / row_size) + nr) && count > 0; i++) {
- address = (i * row_size) + bank->base;
-
- if (count >= row_size) {
- res = samd_write_row(bank, address, buffer + (r * row_size));
- /* Advance one row */
- offset += row_size;
- count -= row_size;
- } else {
- res = samd_write_row_partial(bank, address,
- buffer + (r * row_size), 0, count);
- /* We're done after this. */
- offset += count;
- count = 0;
- }
-
- r++;
-
- if (res != ERROR_OK)
- return res;
- }
- }
+free_pb:
+ if (pb)
+ free(pb);
- return ERROR_OK;
+ return res;
}
FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
return res;
}
+
+
+COMMAND_HANDLER(samd_handle_reset_deassert)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
+ int retval = ERROR_OK;
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
+ * so we just release reset held by DSU
+ *
+ * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
+ *
+ * After vectreset DSU release is not needed however makes no harm
+ */
+ if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+ if (retval == ERROR_OK)
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
+ TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ /* do not return on error here, releasing DSU reset is more important */
+ }
+
+ /* clear CPU Reset Phase Extension bit */
+ int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
+ if (retval2 != ERROR_OK)
+ return retval2;
+
+ return retval;
+}
+
static const struct command_registration at91samd_exec_command_handlers[] = {
+ {
+ .name = "dsu_reset_deassert",
+ .handler = samd_handle_reset_deassert,
+ .mode = COMMAND_EXEC,
+ .help = "deasert internal reset held by DSU"
+ },
{
.name = "info",
.handler = samd_handle_info_command,
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