Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
Fix usage of timeval_ms()
[openocd.git] / src / flash / nor / at91sam4.c
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index f34ca4f6bd0747ddeeaf4cfe5ffb75103019cf29..50aa98b8935438186eda1ab4b9bf6d2340bcc653 100644 (file)
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -9,19 +9,17 @@
  *   (at91sam3x* & at91sam4 support)*                                      *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General public License as published by  *
+ *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
  *   (at your option) any later version.                                   *
  *                                                                         *
  *   This program is distributed in the hope that it will be useful,       *
  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
- *   GNU General public License for more details.                          *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
  *                                                                         *
- *   You should have received a copy of the GNU General public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ****************************************************************************/
 
 /* Some of the the lower level code was based on code supplied by
@@ -67,7 +65,7 @@
 
 #define REG_NAME_WIDTH  (12)
 
-/* at91sam4s series (has always one flash bank)*/
+/* at91sam4s/at91sam4e series (has always one flash bank)*/
 #define FLASH_BANK_BASE_S   0x00400000
 
 /* at91sam4sd series (two one flash banks), first bank address */
@@ -260,6 +258,209 @@ static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
 
 /* these are used to *initialize* the "pChip->details" structure. */
 static const struct sam4_chip_details all_sam4_details[] = {
+
+       /* Start at91sam4e* series */
+       /*atsam4e16e - LQFP144/LFBGA144*/
+       {
+               .chipid_cidr    = 0xA3CC0CE0,
+               .name           = "at91sam4e16e",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 128 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
+       /* Start at91sam4n* series */
+       /*atsam4n8a - LQFP48/QFN48*/
+       {
+               .chipid_cidr    = 0x293B0AE0,
+               .name           = "at91sam4n8a",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n8b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x294B0AE0,
+               .name           = "at91sam4n8b",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
+       {
+               .chipid_cidr    = 0x295B0AE0,
+               .name           = "at91sam4n8c",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  512 * 1024,
+                       .nsectors   =  64,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n16b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x29460CE0,
+               .name           = "at91sam4n16b",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 80 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+       /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
+       {
+               .chipid_cidr    = 0x29560CE0,
+               .name           = "at91sam4n16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 80 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
        /* Start at91sam4s* series */
        /*atsam4s16c - LQFP100/BGA100*/
        {
@@ -327,6 +528,39 @@ static const struct sam4_chip_details all_sam4_details[] = {
                  },
                },
        },
+       /*atsam4sa16b - LQFP64/QFN64*/
+       {
+               .chipid_cidr    = 0x28970CE0,
+               .name           = "at91sam4sa16b",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  1024 * 1024,
+                       .nsectors   =  128,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
        /*atsam4s16a - LQFP48/QFN48*/
        {
                .chipid_cidr    = 0x288C0CE0,
@@ -460,6 +694,40 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
+       /*atsam4s4a - LQFP48/BGA48*/
+       {
+               .chipid_cidr    = 0x288b09e0,
+               .name           = "at91sam4s4a",
+               .total_flash_size     = 256 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  32,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
        /*at91sam4sd32c*/
        {
                .chipid_cidr    = 0x29a70ee0,
@@ -504,6 +772,129 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
+       /*at91sam4sd16c*/
+       {
+               .chipid_cidr    = 0x29a70ce0,
+               .name           = "at91sam4sd16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_1024K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
+       /*at91sam4sa16c*/
+       {
+               .chipid_cidr    = 0x28a70ce0,
+               .name           = "at91sam4sa16c",
+               .total_flash_size     = 1024 * 1024,
+               .total_sram_size      = 160 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+
+/*             .bank[0] = { */
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_1024K_SD,
+                               .controller_address = 0x400e0c00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+               },
+       },
+
+       /* at91samg53n19 */
+       {
+               .chipid_cidr    = 0x247e0ae0,
+               .name           = "at91samg53n19",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 96 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+
+/*             .bank[0] = {*/
+               {
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  512 * 1024,
+                               .nsectors   =  64,
+                               .sector_size = 8192,
+                               .page_size   = 512,
+                       },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               }
+       },
+
        /* terminate */
        {
                .chipid_cidr    = 0,
@@ -662,7 +1053,7 @@ static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
 
        int r;
        uint32_t v;
-       long long ms_now, ms_end;
+       int64_t ms_now, ms_end;
 
        /* default */
        if (status)
@@ -1014,11 +1405,11 @@ static const char *const eproc_names[] = {
        _unknown,                                       /* 0 */
        "arm946es",                                     /* 1 */
        "arm7tdmi",                                     /* 2 */
-       "cortex-m3",                            /* 3 */
+       "Cortex-M3",                            /* 3 */
        "arm920t",                                      /* 4 */
        "arm926ejs",                            /* 5 */
-       "cortex-a5",                            /* 6 */
-       "cortex-m4",                            /* 7 */
+       "Cortex-A5",                            /* 6 */
+       "Cortex-M4",                            /* 7 */
        _unknown,                                       /* 8 */
        _unknown,                                       /* 9 */
        _unknown,                                       /* 10 */
@@ -1076,8 +1467,13 @@ static const struct archnames { unsigned value; const char *name; } archnames[]
        { 0x37,  "CAP7 Series"                                                          },
        { 0x39,  "CAP9 Series"                                                          },
        { 0x3B,  "CAP11 Series"                                                         },
+       { 0x3C, "ATSAM4E"                                                               },
        { 0x40,  "AT91x40 Series"                                                       },
        { 0x42,  "AT91x42 Series"                                                       },
+       { 0x43,  "SAMG51 Series"
+       },
+       { 0x47,  "SAMG53 Series"
+       },
        { 0x55,  "AT91x55 Series"                                                       },
        { 0x60,  "AT91SAM7Axx Series"                                           },
        { 0x61,  "AT91SAM7AQxx Series"                                          },
@@ -1398,7 +1794,7 @@ static const struct sam4_reg_list sam4_all_regs[] = {
 
 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
 {
-       return (struct sam4_bank_private *)(bank->driver_priv);
+       return bank->driver_priv;
 }
 
 /**
@@ -1838,7 +2234,7 @@ static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum,
        return r;
 }
 
-static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
 {
        uint32_t adr;
        uint32_t status;
@@ -1900,7 +2296,7 @@ static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum,
 }
 
 static int sam4_write(struct flash_bank *bank,
-       uint8_t *buffer,
+       const uint8_t *buffer,
        uint32_t offset,
        uint32_t count)
 {
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)