* Copyright (C) 2009 by Duane Ellis *
* openocd@duaneellis.com *
* *
+ * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
+ * olaf@uni-paderborn.de *
+ * *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "imp.h"
-#include "at91sam3.h"
#include <helper/time_support.h>
#define REG_NAME_WIDTH (12)
+// at91sam3u series (has one or two flash banks)
+#define FLASH_BANK0_BASE_U 0x00080000
+#define FLASH_BANK1_BASE_U 0x00100000
-#define FLASH_BANK0_BASE 0x00080000
-#define FLASH_BANK1_BASE 0x00100000
+// at91sam3s series (has always one flash bank)
+#define FLASH_BANK_BASE_S 0x00400000
#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#define offset_EFC_FRR 12
+extern struct flash_driver at91sam3_flash;
+
static float
_tomhz(uint32_t freq_hz)
{
// these are used to *initialize* the "pChip->details" structure.
static const struct sam3_chip_details all_sam3_details[] = {
+ // Start at91sam3u* series
{
.chipid_cidr = 0x28100960,
.name = "at91sam3u4e",
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
- .base_address = FLASH_BANK1_BASE,
+ .base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 64 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
- .base_address = FLASH_BANK1_BASE,
+ .base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 128 * 1024,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
- .base_address = FLASH_BANK0_BASE,
+ .base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
.present = 1,
.size_bytes = 64 * 1024,
},
},
+ // Start at91sam3s* series
+
+ // Note: The preliminary at91sam3s datasheet says on page 302
+ // that the flash controller is at address 0x400E0800.
+ // This is _not_ the case, the controller resides at address 0x400e0a0.
+ {
+ .chipid_cidr = 0x28A00960,
+ .name = "at91sam3s4c",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+
+ {
+ .chipid_cidr = 0x28900960,
+ .name = "at91sam3s4b",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28800960,
+ .name = "at91sam3s4a",
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 48 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 32,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28AA0760,
+ .name = "at91sam3s2c",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x289A0760,
+ .name = "at91sam3s2b",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x288A0760,
+ .name = "at91sam3s2a",
+ .total_flash_size = 128 * 1024,
+ .total_sram_size = 32 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 128 * 1024,
+ .nsectors = 16,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28A90560,
+ .name = "at91sam3s1c",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28990560,
+ .name = "at91sam3s1b",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
+ {
+ .chipid_cidr = 0x28890560,
+ .name = "at91sam3s1a",
+ .total_flash_size = 64 * 1024,
+ .total_sram_size = 16 * 1024,
+ .n_gpnvms = 2,
+ .n_banks = 1,
+ {
+// .bank[0] = {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_S,
+
+ .controller_address = 0x400e0a00,
+ .present = 1,
+ .size_bytes = 64 * 1024,
+ .nsectors = 8,
+ .sector_size = 8192,
+ .page_size = 256,
+ },
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+
+ },
+ },
+ },
// terminate
{
.chipid_cidr = 0,
uint32_t rcen;
v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
- LOG_USER_N("(main xtal enabled: %s)\n",
+ LOG_USER("(main xtal enabled: %s)",
_yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
- LOG_USER_N("(main osc bypass: %s)\n",
+ LOG_USER("(main osc bypass: %s)",
_yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
- LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
+ rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ LOG_USER("(onchip RC-OSC enabled: %s)",
_yes_or_no(rcen));
v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
- LOG_USER_N("(onchip RC-OSC freq: %s)\n",
+ LOG_USER("(onchip RC-OSC freq: %s)",
_rc_freq[v]);
pChip->cfg.rc_freq = 0;
switch (v) {
default:
pChip->cfg.rc_freq = 0;
+ break;
case 0:
pChip->cfg.rc_freq = 4 * 1000 * 1000;
break;
}
v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
- LOG_USER_N("(startup clks, time= %f uSecs)\n",
+ LOG_USER("(startup clks, time= %f uSecs)",
((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
- LOG_USER_N("(mainosc source: %s)\n",
+ LOG_USER("(mainosc source: %s)",
v ? "external xtal" : "internal RC");
v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
- LOG_USER_N("(clock failure enabled: %s)\n",
+ LOG_USER("(clock failure enabled: %s)",
_yes_or_no(v));
}
LOG_USER_N("\n");
v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
- LOG_USER_N("%s\n", eproc_names[v]);
+ LOG_USER("%s", eproc_names[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
- LOG_USER_N("%s\n", nvpsize[v]);
+ LOG_USER("%s", nvpsize[v]);
v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
- LOG_USER_N("%s\n", nvpsize2[v]);
+ LOG_USER("%s", nvpsize2[v]);
v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
- LOG_USER_N("%s\n", sramsize[ v ]);
+ LOG_USER("%s", sramsize[ v ]);
v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown;
}
}
- LOG_USER_N("%s\n", cp);
+ LOG_USER("%s", cp);
v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
- LOG_USER_N("%s\n", nvptype[ v ]);
+ LOG_USER("%s", nvptype[ v ]);
v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
- LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
+ LOG_USER("(exists: %s)", _yes_or_no(v));
}
static void
v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
- LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
+ LOG_USER("(main ready: %s)", _yes_or_no(v));
v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
v = (v * pChip->cfg.slow_freq) / 16;
pChip->cfg.mainosc_freq = v;
- LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
+ LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
_tomhz(v),
pChip->cfg.slow_freq / 1000,
pChip->cfg.slow_freq % 1000);
LOG_USER_N("\n");
pChip->cfg.plla_freq = 0;
if (mula == 0) {
- LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
+ LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
} else if (diva == 0) {
- LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
+ LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
} else if (diva == 1) {
pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
- LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
+ LOG_USER("\tPLLA Freq: %3.03f MHz",
_tomhz(pChip->cfg.plla_freq));
}
}
break;
}
- LOG_USER_N("%s (%3.03f Mhz)\n",
+ LOG_USER("%s (%3.03f Mhz)",
cp,
_tomhz(fin));
pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
case 0:
pdiv = 1;
cp = "selected clock";
+ break;
case 1:
pdiv = 2;
cp = "clock/2";
assert(0);
break;
}
- LOG_USER_N("(%s)\n", cp);
+ LOG_USER("(%s)", cp);
fin = fin / pdiv;
// sam3 has a *SINGLE* clock -
// other at91 series parts have divisors for these.
pChip->cfg.cpu_freq = fin;
pChip->cfg.mclk_freq = fin;
pChip->cfg.fclk_freq = fin;
- LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
+ LOG_USER("\t\tResult CPU Freq: %3.03f",
_tomhz(fin));
}
// By using prototypes - we can detect what would
// be casting errors.
- return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
+ return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
}
// calculate where this one go..
// it is "possibly" this register.
- pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+ pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
// well? Is it this register
if (pPossible == goes_here) {
r = target_read_u32(pChip->target, pReg->address, goes_here);
if (r != ERROR_OK) {
- LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
+ LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
pReg->name, (unsigned)(pReg->address), r);
}
return r;
r = sam3_ReadThisReg(pChip,
sam3_get_reg_ptr(&(pChip->cfg), pReg));
if (r != ERROR_OK) {
- LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
+ LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
pReg->name, ((unsigned)(pReg->address)), r);
return r;
}
// display all regs
LOG_DEBUG("Start: %s", pReg->name);
regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
- LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
+ LOG_USER("%*s: [0x%08x] -> 0x%08x",
REG_NAME_WIDTH,
pReg->name,
pReg->address,
LOG_DEBUG("End: %s", pReg->name);
pReg++;
}
- LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
- LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
- LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
- LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
- LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
+ LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
+ LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
+ LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
+ LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
+ LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
- LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
pChip->cfg.unique_id[0],
pChip->cfg.unique_id[1],
pChip->cfg.unique_id[2],
return ERROR_TARGET_NOT_HALTED;
}
if (0 == bank->num_sectors) {
- LOG_ERROR("Target: not supported/not probed\n");
+ LOG_ERROR("Target: not supported/not probed");
return ERROR_FAIL;
}
switch (bank->base) {
default:
- LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
+ LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
+ [at91sam3u series] or 0x%08x [at91sam3s series])",
((unsigned int)(bank->base)),
- ((unsigned int)(FLASH_BANK0_BASE)),
- ((unsigned int)(FLASH_BANK1_BASE)));
+ ((unsigned int)(FLASH_BANK0_BASE_U)),
+ ((unsigned int)(FLASH_BANK1_BASE_U)),
+ ((unsigned int)(FLASH_BANK_BASE_S)));
return ERROR_FAIL;
break;
- case FLASH_BANK0_BASE:
+
+ // at91sam3u series
+ case FLASH_BANK0_BASE_U:
bank->driver_priv = &(pChip->details.bank[0]);
bank->bank_number = 0;
pChip->details.bank[0].pChip = pChip;
pChip->details.bank[0].pBank = bank;
break;
- case FLASH_BANK1_BASE:
+ case FLASH_BANK1_BASE_U:
bank->driver_priv = &(pChip->details.bank[1]);
bank->bank_number = 1;
pChip->details.bank[1].pChip = pChip;
pChip->details.bank[1].pBank = bank;
+
+ // at91sam3s series
+ case FLASH_BANK_BASE_S:
+ bank->driver_priv = &(pChip->details.bank[0]);
+ bank->bank_number = 0;
+ pChip->details.bank[0].pChip = pChip;
+ pChip->details.bank[0].pBank = bank;
break;
}
LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
// Help the victim, print details about the chip
- LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
+ LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
pPrivate->pChip->cfg.CHIPID_CIDR);
sam3_explain_chipid_cidr(pPrivate->pChip);
return ERROR_FAIL;
pPrivate = get_sam3_bank_private(bank);
if (!pPrivate) {
- LOG_ERROR("Invalid/unknown bank number\n");
+ LOG_ERROR("Invalid/unknown bank number");
return ERROR_FAIL;
}
r = sam3_GetInfo(pChip);
if (r != ERROR_OK) {
- LOG_DEBUG("Sam3Info, Failed %d\n",r);
+ LOG_DEBUG("Sam3Info, Failed %d",r);
return r;
}